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| 22-S3-CB519-032004 USER'S MANUAL S3CB519 8-Bit CMOS Microcontroller Revision 2 S3CB519 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 2 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product. S3CB519 8-Bit CMOS Microcontrollers User's Manual, Revision 2 Publication Number: 22-S3-CB519-042004 (c) 2004 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Kiheung-Eup Yongin-City, Kyunggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(331)-209-1907 FAX: (82)-(331)-209-1899 Home-Page URL: Http://www.samsungsemi.com Printed in the Republic of Korea Preface The S3CB519 Microcontroller User's Manual is designed for application designers and programmers who are using the S3CB519 microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has nine chapters: Chapter 1 Chapter 2 Chapter 3 Chapter 4 Product Overview Address Spaces Registers Memory Map Chapter 5 Chapter 6 Chapter 7 Chapter 8 Hardware Stack Exceptions Coprocessor Interface Instruction Set Chapter 1, "Product Overview," is a high-level introduction to S3CB519 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," describes program and data memory spaces. Chapter 2 also describes ROM code option. Chapter 3, "Register," describes the special registers. Chapter 4, "Memory Map," describes the internal register file. Chapter 5, "Hardware Stack," describes the S3CB519 hardware stack structure in detail. Chapter 6, "Exceptions," describes the S3CB519 exception structure in detail. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the S3CB-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1-3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, 6, 7, 8, and 9. Later, you can reference the information in Part I as necessary. Part II "Hardware descriptions," has detailed information about specific hardware components of the S3CB519 microcontroller. Also included in Part II are electrical, mechanical. It has 16 chapters: Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Clock Circuit nRESET and Power-Down I/O Ports Basic Timer/Watchdog Timer Watch Timer 16-Bit Timer (8-Bit Timer A & B) 8-Bit Timer (Timer 0) Serial I/O Interface Battery Level Detector Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Chapter 24 LCD Controller/Driver A/D Converter D/A Converter MAC 816 Electrical Data Mechanical Data Development Tools Chapter 21, "MAC816" describes the MAC816 structure in detail, as well as instructions. Two order forms are included at the back of this manual to facilitate customer order for S3CB519 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative. S3CB519 MICROCONTROLLER iii Table of Contents Part I -- Programming Model Chapter 1 Product Overview Overview .............................................................................................................................................1-1 Features .............................................................................................................................................1-5 Pin Assignment...................................................................................................................................1-7 I/O Pin Description ..............................................................................................................................1-8 Pin Circuit Diagrams............................................................................................................................1-10 Chapter 2 Address Spaces Overview .............................................................................................................................................2-1 Program Memory (ROM) ......................................................................................................................2-2 ROM Code Option (RCOD_OPT)...........................................................................................................2-5 Data Memory Organization...................................................................................................................2-7 Chapter 3 Registers Overview .............................................................................................................................................3-1 Index Registers: IDH, IDL0 and IDL1..............................................................................................3-2 Link Registers: ILX, ILH and ILL ....................................................................................................3-2 Status Register 0: SR0 ................................................................................................................3-3 Status Register 1: SR1 ................................................................................................................3-4 Chapter 4 Memory Map Overview .............................................................................................................................................4-1 Chapter 5 Hardware Stack Overview .............................................................................................................................................5-1 S3CB519 MICROCONTROLLER v Table of Contents Chapter 6 Exceptions (Continued) Overview .............................................................................................................................................6-1 Hardware Reset...........................................................................................................................6-1 NMI Exception (Edge Sensitive)....................................................................................................6-2 IRQ[0] Exception (Level-Sensitive).................................................................................................6-2 IRQ[1] Exception (Level-Sensitive).................................................................................................6-2 Hardware Stack Full Exception.....................................................................................................6-2 Break Exception..........................................................................................................................6-2 Exceptions (or Interrupts).............................................................................................................6-3 Interrupt Mask Registers ..............................................................................................................6-5 Interrupt Priority Register..............................................................................................................6-6 Chapter 7 Coprocessor Interface Overview .............................................................................................................................................7-1 Chapter 8 Instruction Set Overview .............................................................................................................................................8-1 Glossary.....................................................................................................................................8-1 Instruction Set Map .............................................................................................................................8-2 Quick Reference..................................................................................................................................8-9 Instruction Group Summary ..................................................................................................................8-12 ALU Instructions..........................................................................................................................8-12 Shift/Rotate Instructions ...............................................................................................................8-16 Load Instructions .........................................................................................................................8-18 Branch Instructions......................................................................................................................8-21 Bit Manipulation Instructions.........................................................................................................8-25 Miscellaneous Instruction.............................................................................................................8-26 Pseudo Instructions .............................................................................................................................8-29 vi S3CB519 MICROCONTROLLER Table of Contents (Continued) Part II Hardware Descriptions Chapter 9 Clock Circuit Overview .............................................................................................................................................9-1 System Clock Circuit...................................................................................................................9-1 Chapter 10 nRESET and Power-Down Overview .............................................................................................................................................10-1 Chapter 11 I/O Ports Overview .............................................................................................................................................11-1 Port 0.........................................................................................................................................11-1 Port 1.........................................................................................................................................11-4 Port 2.........................................................................................................................................11-5 Port 3.........................................................................................................................................11-5 Port 4.........................................................................................................................................11-6 Port 5.........................................................................................................................................11-7 Chapter 12 Basic Timer Overview .............................................................................................................................................12-1 Block Diagram ....................................................................................................................................12-2 Chapter 13 Watch Timer Overview .............................................................................................................................................13-1 Watch Timer Circuit Diagram........................................................................................................13-2 Chapter 14 16-Bit Timer (8-Bit Timer A & B) Overview .............................................................................................................................................14-1 Interval timer function ...................................................................................................................14-1 S3CB519 MICROCONTROLLER vii Table of Contents Chapter 15 8-Bit Timer (Timer 0) (Continued) Overview .........................................................................................................................................15-1 Function Description........................................................................................................................15-2 Timer 0 Control Register (T0CON) .....................................................................................................15-3 Block Diagram ................................................................................................................................15-4 Chapter 16 Serial I/O Interface Overview .............................................................................................................................................16-1 Programming Procedure...............................................................................................................16-1 SIO Control Register (SIOCON) ....................................................................................................16-2 SIO Pre-Scaler Register (SIOPS)..................................................................................................16-3 Block Diagram ....................................................................................................................................16-3 Serial I/O Timing Diagrams...........................................................................................................16-4 Chapter 17 Battery Level Detector Overview .............................................................................................................................................17-1 Chapter 18 LCD Controller/Driver Overview .............................................................................................................................................18-1 LCD RAM Address Area ..............................................................................................................18-1 LCD RAM (RAM Bank 12)............................................................................................................18-1 LCD Control Register (LCON) .......................................................................................................18-2 LCD Voltage Dividing Resistors.....................................................................................................18-2 LCD Mode Register (LMOD) .........................................................................................................18-3 LCD Contrast Control Register (LCNST).........................................................................................18-4 LCD Key Scan ............................................................................................................................18-8 Chapter 19 A/D Converter Overview .............................................................................................................................................19-1 Features .............................................................................................................................................19-1 A/D Converter Control Register (ADCON).......................................................................................19-2 Chapter 20 D/A Converter Overview .............................................................................................................................................20-1 D/A Converter Data Register (DADATA).........................................................................................20-3 D/A Converter Control Register (DACON).......................................................................................20-3 viii S3CB519 MICROCONTROLLER Table of Contents Chapter 21 MAC816 (Concluded) MAC816 Architecture Overview .............................................................................................................21-1 Programmer's Model............................................................................................................................21-3 Data Memory Accesses...............................................................................................................21-3 Computation Unit.........................................................................................................................21-7 Status Registers .........................................................................................................................21-9 Host Interface..............................................................................................................................21-11 Instruction Set.....................................................................................................................................21-14 Glossary.....................................................................................................................................21-14 Instruction Encoding ....................................................................................................................21-20 Quick Reference..........................................................................................................................21-22 MAC816 Instruction Description....................................................................................................21-25 Chapter 22 Electrical Data Overview............................................................................................................................................22-1 Chapter 23 Mechanical Data Overview .............................................................................................................................................23-1 Chapter 24 Development Tools Overview .............................................................................................................................................24-1 CALMSHINE: IDE(Integrated Development Environment).....................................................................24-1 Invisible MDS: In-Circuit Emulator .....................................................................................................24-1 CALMRISC8 C-Compiler: CALM8CC .................................................................................................24-1 CALMRISC8 Relocatable Assembler: CALM8ASM.............................................................................24-1 CALMRISC8 Linker: CALM8LINK ......................................................................................................24-1 Emulation Probe Board Configuration ....................................................................................................24-2 External Event Input Headers (JP4) ...................................................................................................24-3 Event Match Output Headers (JP9) ...................................................................................................24-3 External Break Input Headers (TP4) ..................................................................................................24-3 A/D Converter Function Block...............................................................................................................24-4 Communication Selection.................................................................................................................24-5 Use Clock Setting for External Clock Mode........................................................................................24-5 Sub Clock Setting ...........................................................................................................................24-5 CN1, CN2 Pin Assignment ...............................................................................................................24-6 S3CB519 MICROCONTROLLER ix List of Figures Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 2-1 2-2 2-3 2-4 2-5 2-6 3-1 4-1 5-1 5-2 5-3 5-4 5-5 Title Page Number Top Block Diagram ..............................................................................................1-2 CalmRISC Pipeline Diagram .................................................................................1-3 CalmRISC Pipeline Stream Diagram......................................................................1-4 S3CB519 Block Diagram......................................................................................1-6 S3CB519 Pin Assignment Diagram (100-QFP).......................................................1-7 S3CB519 Pin Assignment Diagram (100-TQFP).....................................................1-8 Pin Circuit Type B ...............................................................................................1-11 Pin Circuit Type C ...............................................................................................1-11 Pin Circuit Type E-2.............................................................................................1-11 Pin Circuit Type D-2.............................................................................................1-11 Pin Circuit Type H-29...........................................................................................1-12 Pin Circuit Type H-35...........................................................................................1-12 Pin Circuit Type H-34...........................................................................................1-12 Pin Circuit Type F-10 ...........................................................................................1-12 Program Memory Address Space .........................................................................2-2 Relative Jump Around Page Boundary ...................................................................2-3 Program Memory Layout ......................................................................................2-4 ROM Code Option (RCOD_OPT)...........................................................................2-6 Data Memory Map...............................................................................................2-7 S3CB519 Data Memory Map ................................................................................2-8 Bank Selection by Setting of GRB Bits and IDB Bit ................................................3-3 Control Register Area...........................................................................................4-1 Hardware Stack...................................................................................................5-1 Even and Odd Bank Selection Example.................................................................5-2 Stack Operation with PC [19:0].............................................................................5-3 Stack Operation with Registers.............................................................................5-4 Stack Overflow ....................................................................................................5-5 S3CB519 MICROCONTROLLER xi List of Figures (Continued) Figure Number 6-1 6-2 6-3 6-4 7-1 7-2 9-1 9-2 9-3 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 12-1 12-2 13-1 14-1 14-2 14-3 15-1 15-2 16-1 16-2 16-3 16-4 16-5 17-1 17-2 Title Page Number Interrupt Structure................................................................................................6-3 Interrupt Structure................................................................................................6-4 Interrupt Mask Register........................................................................................6-5 Interrupt Priority Register......................................................................................6-6 Coprocessor Interface Diagram .............................................................................7-1 Coprocessor Instruction Pipeline...........................................................................7-3 System Clock Circuit Diagram..............................................................................9-2 Power Control Register (PCON) ............................................................................9-3 Oscillator Control Register (OSCCON)...................................................................9-3 Port 0 Low-byte Control Register (P0CONL)...........................................................11-1 Port 0 High-byte Control Register (P0CONH)..........................................................11-2 Port 0 Interrupt Control Register (P0INT) ................................................................11-2 Port 0 Interrupt Edge Control Register (P0EDGE)...................................................11-3 Port 1 Control Register (P1CON)...........................................................................11-4 Port 1 Interrupt Control Register (P1INT) ................................................................11-4 Port 2 Control Register (P2CON)...........................................................................11-5 Port 3 Control Register (P3CON)...........................................................................11-5 Port 4 Control Register (P4CON)...........................................................................11-6 Port 5 Control Register (P5CON)...........................................................................11-7 Watchdog Timer Control Register (WDTCON) ........................................................12-1 Basic Timer & Watchdog Timer Functional Block Diagram ......................................12-2 Watch Timer Circuit Diagram................................................................................13-2 Timer A Control Register (TACON) ........................................................................14-1 Timer B Control Register (TBCON) ........................................................................14-2 Timer A, B Function Block Diagram ......................................................................14-3 Timer 0 Control Register (T0CON) .........................................................................15-3 Timer 0 Functional Block Diagram.........................................................................15-4 Serial I/O Control Register (SIOCON) ....................................................................16-2 SIO Pre-scaler Register (SIOPS) ..........................................................................16-3 SIO Functional Block Diagram..............................................................................16-3 Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0).................16-4 Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) .................16-4 Voltage Level Detection Circuit .............................................................................17-1 Battery Level Detector Control Register (BLDCON) .................................................17-2 xii S3CB519 MICROCONTROLLER List of Figures (Concluded) Figure Number 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 19-1 19-2 19-3 20-1 20-2 20-3 21-1 21-2 21-3 21-4 21-5 21-6 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 23-1 23-2 24-1 24-2 Title Page Number LCD Display Data RAM Organization ....................................................................18-1 LCD Control Register (LCON) ...............................................................................18-2 Internal Voltage Dividing Resistor Connection.........................................................18-2 LCD Mode Register (LMOD) .................................................................................18-3 LCD Contrast Register (LCNST) ............................................................................18-4 LCD Signal Waveforms (1/16 Duty, 1/5 Bias) .........................................................18-5 LCD Signal Waveforms (1/8 Duty, 1/4 Bias)...........................................................18-7 LCD Waveform when Key Strobe Signal is Active ...................................................18-9 A/DC Control Register (ADCON) ...........................................................................19-2 A/D Converter Block Diagram ...............................................................................19-3 Application Example............................................................................................19-4 D/A Converter Circuit Diagram ..............................................................................20-1 D/A Converter Timing Diagram ..............................................................................20-2 D/A Control Register (DACON) .............................................................................20-3 Top Block Diagram ..............................................................................................21-1 Data Memory Organization...................................................................................21-3 RPU (RAM Pointer Unit) Block Diagram ................................................................21-4 Computation Unit Block Diagram ..........................................................................21-7 Coprocessor Interface Diagram .............................................................................21-11 Coprocessor Instruction Pipeline...........................................................................21-13 Input Timing for External Interrupts (Port 0, Port 1)..................................................22-4 Input Timing for nRESET......................................................................................22-4 Stop Mode Release Timing When Initiated by a nRESET........................................22-5 Stop Mode(Main) Release Timing Initiated by Interrupts ..........................................22-6 Stop Mode(Sub) Release Timing Initiated by Interrupts............................................22-6 Serial Data Transfer Timing...................................................................................22-7 Clock Timing Measurement at XIN .........................................................................22-11 Operating Voltage Range .....................................................................................22-12 100-QFP-1420C Package Dimensions...................................................................23-2 100-TQFP-1414 Package Dimensions ...................................................................23-3 Emulation Probe Board Configuration ....................................................................24-2 A/D converter Function Block Diagram ..................................................................24-4 S3CB519 MICROCONTROLLER xiii List of Tables Table Number 1-1 3-1 3-2 3-3 4-1 6-1 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 13-1 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 Title Page Number S3CB519 Pin Descriptions ...................................................................................1-9 General and Special Purpose Registers.................................................................3-1 Status Register 0 Configuration.............................................................................3-3 Status Register 1: SR1 ........................................................................................3-4 Control Registers.................................................................................................4-2 Exceptions .........................................................................................................6-1 Coprocessor instructions......................................................................................7-2 Instruction Notation Conventions ...........................................................................8-1 Overall Instruction Set Map...................................................................................8-2 Instruction Encoding ............................................................................................8-4 Index Code Information ("idx") ...............................................................................8-7 Index Modification Code Information ("mod") ...........................................................8-7 Condition Code Information ("cc") ..........................................................................8-7 "ALUop1" Code Information...................................................................................8-8 "ALUop2" Code Information...................................................................................8-8 "MODop1" Code Information..................................................................................8-8 Watch Timer Control Register (WTCON): 8-Bit R/W................................................13-1 RPU(RAM Pointer Unit) Registers .........................................................................21-4 RPi register bit information ...................................................................................21-5 Coprocessor instructions......................................................................................21-12 Notation and Convention.......................................................................................21-14 MAC816 Registers ..............................................................................................21-15 Data Transfer Registers........................................................................................21-16 Memory Access Mode Information ........................................................................21-17 Condition Code Information...................................................................................21-18 Control Bit Code Information .................................................................................21-18 AU operation code information ..............................................................................21-19 Others ................................................................................................................21-19 Instruction Encoding ............................................................................................21-20 Quick Reference..................................................................................................21-22 S3CB519 MICROCONTROLLER xv List of Tables (Continued) Table Number 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 22-10 22-11 22-12 Title Page Number Absolute Maximum Ratings..................................................................................22-1 D.C. Electrical Characteristics..............................................................................22-1 A.C. Electrical Characteristics..............................................................................22-4 Data Retention Supply Voltage in Stop Mode.........................................................22-5 Synchronous SIO Electrical Characteristics...........................................................22-7 BLD Electrical Characteristics ..............................................................................22-8 ADC Electrical Characteristics..............................................................................22-8 DAC Electrical Characteristics..............................................................................22-9 Main Oscillator Frequency (fOSC1).........................................................................22-10 Main Oscillator Clock Stabilization Time (TST1) ......................................................22-10 Sub Oscillator Frequency (fOSC2) ..........................................................................22-11 Sub Oscillator(Crystal) Start up Time (t ST2)............................................................22-11 xvi S3CB519 MICROCONTROLLER List of Programming Tips Description Chapter 2: Address Space Page Number Using the Page Pointer for RAM clear (Page 0, Page 1)......................................................................2-5 Setting the Register Pointers ............................................................................................................2-9 Using the RPs to Calculate the Sum of a Series of Registers ..............................................................2-10 Addressing the Common Working Register Area ................................................................................2-14 Standard Stack Operations Using PUSH and POP.............................................................................2-19 Chapter 6: Exceptions Interrupt Programming Tip 1..............................................................................................................6-7 Interrupt Programming Tip 2..............................................................................................................6-8 S3CB519 MICROCONTROLLER xvii List of Instruction Descriptions Instruction Mnemonic ADC ADD AND AND SR0 BANK BITC BITR BITS BITT BMC/BMS CALL CALLS CLD CLD COM COM2 COMC COP CP CPC DEC DECC DI EI IDLE INC INCC IRET JNZD JP JR LCALL LD adr:8 Full Register Name Page Number Add with Carry ....................................................................................................8-30 Add....................................................................................................................8-31 Bit-wise AND ......................................................................................................8-32 Bit-wise AND with SR0Call Procedure ...................................................................8-33 Bank Selection....................................................................................................8-34 Bit Complement ..................................................................................................8-35 Bit Reset ............................................................................................................8-36 Bit Set................................................................................................................8-37 Bit Test ..............................................................................................................8-38 TF bit clear/set ....................................................................................................8-39 Conditional subroutine call (Pseudo Instruction) .....................................................8-40 Call Subroutine....................................................................................................8-41 Load into Coprocessor .........................................................................................8-42 Load from Coprocessor ........................................................................................8-43 1's or Bit-wise Complement ..................................................................................8-44 2's Complement ..................................................................................................8-45 Bit-wise Complement with Carry ...........................................................................8-46 Coprocessor .......................................................................................................8-47 Compare.............................................................................................................8-48 Compare with Carry .............................................................................................8-49 Decrement ..........................................................................................................8-50 Decrement with Carry ..........................................................................................8-51 Disable Interrupt (Pseudo Instruction) ....................................................................8-52 Enable Interrupt (Pseudo Instruction) ....................................................................8-53 Idle Operation (Pseudo Instruction) .......................................................................8-54 Increment ...........................................................................................................8-55 Increment with Carry ............................................................................................8-56 Return from Interrupt Handling...............................................................................8-57 Jump Not Zero with Delay Slot ..............................................................................8-58 Conditional Jump (Pseudo Instruction) ..................................................................8-59 Conditional Jump Relative.....................................................................................8-60 Conditional Subroutine Call...................................................................................8-61 Load into Memory................................................................................................8-62 S3CB519 MICROCONTROLLER xix List of Instruction Descriptions (Continued) Instruction Mnemonic LD @idm LD LD LD LD LD SPR LD SPR0 LDC LJP LLNK LNK LNKS LRET NOP OR OR SR0 POP POP PUSH RET RL RLC RR RRC SBC SL SLA SR SRA STOP SUB SWAP SYS TM XOR Full Instruction Name Page Number Load into Memory Indexed ...................................................................................8-63 Load Register......................................................................................................8-64 Load GPR:bankd, GPR:banks ..............................................................................8-65 Load GPR, TBH/TBL............................................................................................8-66 Load TBH/TBL, GPR............................................................................................8-67 Load SPR...........................................................................................................8-68 Load SPR0 Immediate.........................................................................................8-69 Load Code ..........................................................................................................8-70 Conditional Jump.................................................................................................8-71 Linked Subroutine Call Conditional ........................................................................8-72 Linked Subroutine Call (Pseudo Instruction) ..........................................................8-73 Linked Subroutine Call .........................................................................................8-74 Return from Linked Subroutine Call .......................................................................8-75 No Operation.......................................................................................................8-76 Bit-wise OR ........................................................................................................8-77 Bit-wise OR with SR0 ..........................................................................................8-78 POP...................................................................................................................8-79 POP to Register..................................................................................................8-80 Push Register .....................................................................................................8-81 Return from Subroutine ........................................................................................8-82 Rotate Left ..........................................................................................................8-83 Rotate Left with Carry ..........................................................................................8-84 Rotate Right........................................................................................................8-85 Rotate Right with Carry ........................................................................................8-86 Subtract with Carry ..............................................................................................8-87 Shift Left .............................................................................................................8-88 Shift Left Arithmetic .............................................................................................8-89 Shift Right...........................................................................................................8-90 Shift Right Arithmetic...........................................................................................8-91 Stop Operation (Pseudo Instruction) .....................................................................8-92 Subtract .............................................................................................................8-93 Swap..................................................................................................................8-94 System ..............................................................................................................8-95 Test Multiple Bits ................................................................................................8-96 Exclusive OR ......................................................................................................8-97 xx S3CB519 MICROCONTROLLER S3CB519 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3CB519 single-chip CMOS microcontroller is designed for high performance using Samsung's new 8-bit CPU core, CalmRISC. CalmRISC is an 8-bit low power RISC microcontroller. Its basic architecture follows Harvard style, that is, it has separate program memory and data memory. Both instruction and data can be fetched simultaneously without causing a stall, using separate paths for memory access. Represented below is the top block diagram of the CalmRISC microcontroller. 1-1 PRODUCT OVERVIEW S3CB519 20 PA[19:0] PD[15:0] Program Memory Address Generation Unit PC[19:0] 20 8 8 HS[0] Hardware Stack TBH DO[7:0] TBL HS[15] ABUS[7:0] BBUS[7:0] DI[7:0] ALUL ALUR R0 R1 R2 ALU Flag R3 GPR RBUS SR1 ILX Data Memory Address Generation Unit ILH SR0 ILL IDL0 DA[15:0] IDH IDL1 SPR Figure 1-1. Top Block Diagram 1-2 S3CB519 PRODUCT OVERVIEW The CalmRISC building blocks consist of: -- An 8-bit ALU -- 16 general purpose registers (GPR) -- 11 special purpose registers (SPR) -- 16-level hardware stack -- Program memory address generation unit -- Data memory address generation unit Sixteen GPRs are grouped into four banks (Bank0 to Bank3), and each bank has four 8-bit registers (R0, R1, R2, and R3). SPRs, designed for special purposes, include status registers, link registers for branch-link instructions, and data memory index registers. The data memory address generation unit provides the data memory address (denoted as DA[15:0] in the top block diagram) for a data memory access instruction. Data memory contents are accessed through DI[7:0] for read operations and DO[7:0] for write operations. The program memory address generation unit contains a program counter, PC[19:0], and supplies the program memory address through PA[19:0] and fetches the corresponding instruction through PD[15:0] as the result of the program memory access. CalmRISC has a 16-level hardware stack for low power stack operations as well as a temporary storage area. Instruction Fetch (IF) Instruction Decode/ Data Memory Access (ID/MEM) Execution/Writeback (EXE/WB) Figure 1-2. CalmRISC Pipeline Diagram CalmRISC has a 3-stage pipeline as described below: As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data memory where R is a GPR can be one operand of an ALU instruction as shown below: The first stage (or cycle) is the Instruction fetch stage (IF for short), where the instruction pointed by the program counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is the Instruction Decode and Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and data memory access is performed, if necessary. The final stage is the Execute and Write-back stage (EXE/WB), where the required ALU operation is executed and the result is written back into the destination registers. Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction is completely finished but is performed immediately after completing the current instruction fetch. The pipeline stream of instructions is illustrated in the following diagram. 1-3 PRODUCT OVERVIEW S3CB519 /1 IF /2 ID/MEM IF /3 EXE/WB ID/MEM IF /4 EXE/WB ID/MEM IF EXE/WB IF /5 ID/MEM IF /6 EXE/WB ID/MEM IF EXE/WB ID/MEM EXE/WB Figure 1-3. CalmRISC Pipeline Stream Diagram Most CalmRISC instructions are 1-word instructions, while same branch instructions such as long "call" and "jp" instructions are 2-word instructions. In Figure 1-3, the instruction, I4, is a long branch instruction, and it takes two clock cycles to fetch the instruction. As indicated in the pipeline stream, the number of clocks per instruction (CPI) is 1 except for long branches, which take 2 clock cycles per instruction. 1-4 S3CB519 PRODUCT OVERVIEW FEATURES CPU * * * * 8, 12 and 16 COM selectable 16-level contrast control Key strobe output function 8-bit CalmRISC Coprocessor * * * MAC 816 8 x 16, 16 x 16 multiply and accumulation Arithmetic operation Battery Level Detector * * 2.4, 2.7, 3.0, 3.3, 4.0, 4.5 V detectable Internal level and/or external level selectable Memory * * 8-Bit Serial I/O Interface * * * ROM: 16K-word RAM: 3K-byte 2048 (X-memory) 1024 (Y-memory) 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable A/D Converter I/O Pins * * * * * * Sigma delta ADC Linear 14-bit data (16-bit format) 256X over sampling Operation voltage: VDD = 3.0 V-5.5 V 11 I/O: not include COM/SEG 35 I/O: include COM/SEG Power-Down * * * Idle mode: only CPU clock stops Stop mode: main system oscillator stops Sub-system clock stop mode D/A Converter * * * 8-bit resolution Regulated output voltage Operation voltage: VDD = 2.4 V-5.5 V ROM Option * * Basic timer counter clock source selection reset value Watchdog timer enable/disable selection Oscillation Sources * * * * Crystal, ceramic, RC for main system clock Crystal or external oscillator for subsystem clock Main system clock frequency: Max 8.2 MHz Subsystem clock frequency: 32.768 kHz 8-Bit Basic Timer * * Programmable interval timer 8 kinds of clock source Watchdog Timer * Operating Voltage * System reset 2.2 V to 5.5 V Watch Timer * * Operating Temperature Range * Real time clock or interval time measurement Buzzer function (0.5/1/2/4 kHz at 4.19 MHz OSC) - 25 C to 85 C Package Type * Timer/Counters * * 100-QFP-1420C, 100-TQFP-1414 One 8-bit timer with PWM/Capture One 16-bit general-purpose timer/counter LCD Controller/Driver * 56 SEG x 16 COM terminals 1-5 PRODUCT OVERVIEW S3CB519 XIN XOUT XTIN XTOUT Main OSC SUB OSC WDT Basic Timer SIO P5.0-P5.15 Port 5 CalmRISC CPU Timer 0 P4.0-P4.7 Port 4 Timer 1 SI S0 SCK T0/T0CAP/ T0PWM T0CK Timer A P3.0-P3.7 Port 3 Timer B Watch Timer TACK TB BUZ P2.0-P2.7 Port 2 X-Memory 2048 Bytes Y-Memory 1024 Bytes Control Register 128 Bytes BLD BLD P1.0-P1.3 Port 1 MAC 816 CODEC AVDD AVSS ADINP ADINN ADGAIN DAOUT AVREFOUT REFH REFL P0.0-P0.6 Port 0 COM0-COM15 LCD Driver/Controller SEG0-SEG55 Figure 1-4. S3CB519 Block Diagram 1-6 S3CB519 PRODUCT OVERVIEW PIN ASSIGNMENT 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 COM8/P4.0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 COM9/P4.1 COM10/P4.2 COM11/P4.3 COM12/P4.4 COM13/P4.5 COM14/P4.6 COM15/P4.7 P0.0/INT0/TB P0.1/INT1/T0/T0CAP/T0PWM P0.2/INT2/T0CK/BUZ P0.3/INT3/TACK/BLD P0.4/INT4/nSCK P0.5/INT5/SO P0.6/INT6/SI VDD VSS XOUT XIN TEST XTIN XTOUT nRESET DAOUT AVDD AVSS ADINP ADINN ADGAIN AVREFOUT REFH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P5.15 SEG25/P5.14 SEG26/P5.13 SEG27/P5.12 SEG28/P5.11 SEG29/P5.10 SEG30/P5.9 SEG31/P5.8 SEG32/P5.7 SEG33/P5.6 SEG34/P5.5 SEG35/P5.4 SEG36/P5.3 SEG37/P5.2 SEG38/P5.1 SEG39/P5.0 SEG40/P3.7 Figure 1-5. S3CB519 Pin Assignment Diagram (100-QFP) REFL P1.0/KS0 P1.1/KS1 P1.2/KS2 P1.3/KS3 P2.0/SEG55 P2.1/SEG54 P2.2/SEG53 P2.3/SEG52 P2.4/SEG51 P2.5/SEG50 P2.6/SEG49 P2.7/SEG48 P3.0/SEG47 P3.1/SEG46 P3.2/SEG45 P3.3/SEG44 P3.4/SEG43 P3.5/SEG42 P3.6/SEG41 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (100-QFP-1420C) S3CB519 1-7 PRODUCT OVERVIEW S3CB519 COM11/P4.3 COM12/P4.4 COM13/P4.5 COM14/P4.6 COM15/P4.7 P0.0/INT0/TB P0.1/INT1/T0/T0CAP/T0PWM P0.2/INT2/T0CK/BUZ P0.3/INT3/TACK/BLD P0.4/INT4/nSCK P0.5/INT5/SO P0.6/INT6/SI VDD VSS XOUT XIN TEST XTIN XTOUT nRESET DAOUT AVDD AVSS ADINP ADINN 1 2 3 4 5 6 7 8 9 10 11 (SDAT) 12 (SCLK) 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 COM10/P4.2 COM9/P4.1 COM8/P4.0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 S3FB519 (100-TQFP-1414) SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P5.15 SEG25/P5.14 SEG26/P5.13 SEG27/P5.12 SEG28/P5.11 SEG29/P5.10 SEG30/P5.9 SEG31/P5.8 SEG32/P5.7 SEG33/P5.6 SEG34/P5.5 SEG35/P5.4 SEG36/P5.3 SEG37/P5.2 SEG38/P5.1 Figure 1-6. S3CB519 Pin Assignment Diagram (100-TQFP) 1-8 ADGAIN AVREFOUT REFH REFL P1.0/KS0 P1.1/KS1 P1.2/KS2 P1.3/KS3 P2.0/SEG55 P2.1/SEG54 P2.2/SEG53 P2.3/SEG52 P2.4/SEG51 P2.5/SEG50 P2.6/SEG49 P2.7/SEG48 P3.0/SEG47 P3.1/SEG46 P3.2/SEG45 P3.3/SEG44 P3.4/SEG43 P3.5/SEG42 P3.6/SEG41 P3.7/SEG40 P5.0/SEG39 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 S3CB519 PRODUCT OVERVIEW I/O PIN DESCRIPTION Table 1-1. S3CB519 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P1.0-P1.3 I/O Pin Type I/O Pin Description I/O port with bit programmable pins; Input and output modes can be selected by software; Software assignable pull-up. Alternately, P0.0-P0.6 can be used as INT0-INT6, TB, T0, T0CAP, T0PWM, T0CK, BUZ, TACK, BLD, nSCK, SO, SI. Circuit Type D-2 D-2 D-2 F-10 D-2 D-2 D-2 D-2 Share Pins INT0/TB INT1/T0/T0CAP/T 0PWM INT2/T0CK/BUZ INT3/TACK/BLD INT4/nSCK INT5/SO INT6/SI KS0-KS3 I/O port with bit programmable pins; Input and output modes can be selected by software; Software assignable pull-up. Alternately, P1.0-P1.3 can be used as KS0-KS3. I/O port with 4-bit programmable pins; Input and output modes can be selected by software; Software assignable pullup. Alternately, P2.0-P2.7 can be used as SEG55-SEG48. I/O port with 4-bit programmable pins; Input and output modes can be selected by software; Software assignable pullup. Alternately, P3.0-P3.7 can be used as SEG47-SEG40. I/O port with 4-bit programmable pins; Input and output modes can be selected by software; Software assignable pullup. Alternately, P4.0-P4.7 can be used as COM8-COM15. Key strobe output port with 4-bit programmable pins. Push-pull and open-drain modes can be selected by software. Alternately, P5.0-P5.15 can be used as SEG39-SEG24. LCD segment signal output. P2.0-P2.7 I/O H-35 SEG55-SEG48 P3.0-P3.7 I/O H-35 SEG47-SEG40 P4.0-P4.7 I/O H-35 COM8-COM15 P5.0-P5.15 O H-34 SEG39-SEG24 SEG0- SEG23 SEG24- SEG39 SEG40- SEG55 COM0- COM7 COM8- COM15 KS0-KS3 INT0-INT2, INT4-INT6 INT3 O O I/O O O I/O I/O I/O H-29 H-34 H-35 - P5.0-P5.15 P3.0-P3.7 P2.0-P2.7 - P4.0-P4.7 P1.0-P1.3 P0.0-P0.2, P0.4-P0.6 P0.3 LCD common signal output. H-29 H-35 Key interrupt and/or external interrupt inputs. External interrupt input. D-2 D-2 F-10 1-9 PRODUCT OVERVIEW S3CB519 Table 1-1. S3CB519 Pin Descriptions (Continued) Pin Name TB T0 T0CAP T0PWM T0CK BUZ TACK BLD nSCK SO SI DAOUT AVDD AVSS ADINP ADINN ADGAIN AVREFOUT REFH REFL VDD VSS XIN, XOUT XTIN, XTOUT TEST nRESET Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O - - I I - O - - - - - - I I Timer B clock output. Timer 0 clock output. Timer 0 capture input. Timer 0 PWM output. Timer 0 clock input. Buzzer output. Timer A clock input. Battery level detector input. Serial I/O interface clock signal. Serial data output. Serial data input. DAC analog output. Analog power. Analog ground. Analog input positive. Analog input negative. Analog input gain control. Analog reference voltage output. Analog reference power. Analog reference ground. Main power supply. Ground Crystal, Ceramic or RC oscillator pins for system clock. Crystal oscillator pins for subsystem clock. Chip test input pin. Hold GND with the device is operating. Reset signal Pin Description Circuit Type D-2 D-2 D-2 D-2 D-2 D-2 F-10 F-10 D-2 D-2 D-2 - - - - - - - - - - - - - - B P0.0 P0.1 P0.1 P0.1 P0.2 P0.2 P0.3 P0.3 P0.4 P0.5 P0.6 - - - - - - - - - - - - - - - Share Pins 1-10 S3CB519 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD Pull-Up Resistor In Pull-up Enable Open drain Enable Data Output Figure 1-7. Pin Circuit Type B Figure 1-9. Pin Circuit Type E-2 VDD VDD Pull-up Enable Data Data Out Output Disable Output Disable Pin Circuit Type C I/O Ext. INT Noise Filter Input Figure 1-8. Pin Circuit Type C Figure 1-10. Pin Circuit Type D-2 1-11 PRODUCT OVERVIEW S3CB519 VLC1 Open drain enable VLC2/VLC3 Out VDD Output disable Output Data VLC4/VLC5 COM/SEG VSS Pin Circuit Type H-29 Figure 1-11. Pin Circuit Type H-29 Figure 1-13. Pin Circuit Type H-34 VDD VDD Pull-up Enable Data Output Disable COM/SEG Pin Circuit Type E-2 Data Output Disable Pin Circuit Type C I/O Pin Circuit Type H-29 I/O Ext. INT Noise Filter Input Input Analog (BLD) Figure 1-12. Pin Circuit Type H-35 Figure 1-14. Pin Circuit Type F-10 1-12 S3CB519 ADDRESS SPACE 2 OVERVIEW ADDRESS SPACE CalmRISC has 20-bit program address lines, PA[19:0], which support up to 1 Mwords of program memory. The 1 Mword program memory space is divided into 256 pages, and each page is 4 Kwords long as shown on the next page. The upper 8 bits of the program counter, PC[19:12], points to a specific page, and the lower 12 bits, PC[11:0], specify the offset address of the page. CalmRISC also has 16-bit data memory address lines, DA[15:0], which support up to 64K-byte of data memory. The 64K-byte data memory space is divided into 256 pages, and each page has 256 bytes. The upper 8 bits of the data address, DA[15:8], points to a specific page, and the lower 8 bits, DA[7:0], specify the offset address of the page. 2-1 ADDRESS SPACE S3CB519 PROGRAM MEMORY (ROM) FFFH 1 Mword FFFH 4 Kword 00H 256 page 00H Figure 2-1. Program Memory Organization For example, if PC[19:0] = 5F79AH, the page index pointed to by PC is 5FH, and the offset in the page is 79AH. If the current PC[19:0] = 5EFFFH and the instruction pointed to by the current PC (i.e., the instruction at the address 5EFFFH is not a branch instruction), the next PC becomes 5E000H, not 5F000H. In other words, the instruction sequence wraps around at the page boundary, unless the instruction at the boundary (in the above example, at 5EFFFH) is a long branch instruction. The only way to change the program page is by long branches (CALL, LNK, and JP), where the absolute branch target address is specified. For example, if the current PC[19:0] = 047ACH (the page index is 04H and the offset is 7ACH) and the instruction pointed to by the current PC (i.e., the instruction at the address 047ACH), is "JP A507FH" (jump to the program address A507FH) , then the next PC[19:0] = A507FH, which means that the page and the offset are changed to A5H and 07FH, respectively. On the other hand, the short branch instructions cannot change the page indices. 2-2 S3CB519 ADDRESS SPACE Suppose the current PC is 6FFFEH and its instruction is "JR 5H" (jump to the program address PC + 5H), then the next instruction address is 6F003H, not 70003H. In other words, the branch target address calculation also wraps around with respect to a page boundary. This situation is illustrated below: Page 6FH 000H 001H 002H 003H 004H 005H FFEH FFFH JR 5H Figure 2-2. Relative Jump Around Page Boundary Programmers do not have to manually calculate the offset and insert extra instructions for a jump instruction across page boundaries. The compiler and the assembler for CalmRISC are in charge of producing appropriate codes for them. 2-3 ADDRESS SPACE S3CB519 FFFFFH ~ ~ Program Memory Area (1M-word) 4000H 3FFFH 16K-word 00020H 0001FH Vector and Option Area 00000H NOTE: S3CB519 has totally 16K-word (32K-byte) program memory area. Figure 2-3. Program Memory Layout From 00000H to 00004H addresses are used for vector addresses of exceptions, and 0001EH and 0001FH are used for only the option. Aside from these addresses others are reserved in the vector and option area. Program memory area from the address 00020H to FFFFFH can be used for normal programs. Because the S3CB519's program memory is 16 Kword (32K-byte), the block of addresses from 00020H to 3FFFH is the program memory area. 2-4 S3CB519 ADDRESS SPACE ROM CODE OPTION (RCOD_OPT) Just after power on, the ROM data located at 0001EH and 0001FH is used as the ROM code option. S3CB519 has ROM code options like the Reset value of Basic timer and Watchdog timer enable. For example, if you program as below: opt_sec section opt_sec dw 3FFH CODE, abs 0001FH -- fxx/32 is used as Reset value of basic timer (by bit.14, 13, 12) -- Watch-dog timer is enabled (by bit.11) If you don't program any values in these option areas, then the default value is "1". In these cases, the address 0001EH would be the value of "FFFFH". 2-5 ADDRESS SPACE S3CB519 ROM_Code Option (RCOD_OPT) ROM Address: 0001FH MSB .15 .14 .13 .12 .11 .10 .9 .8 LSB Not used Reset value of basic timer clock selection bits (WDTCON.6, .5, .4): 000 = fxx/2 Not used 001 = fxx/4 010 = fxx/16 011 = fxx/32 Watchdog timer enable selection bit: 100 = fxx/128 0 = Disable WDT 101 = fxx/256 1 = Enable WDT 110 = fxx/1024 111 = fxx/2048 Not used (Watchdog timer clock input is basic timer overflow) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used ROM Address: 0001EH MSB .15 .14 .13 .12 .11 .10 .9 .8 LSB Not used MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Figure 2-4. ROM Code Option (RCOD_OPT) 2-6 S3CB519 ADDRESS SPACE DATA MEMORY ORGANIZATION The total data memory address space is 64K-byte, addressed by DA[15:0], and divided into 256 pages, Each page consists of 256 bytes as shown below. FFH 64 KByte FFH FFFH FFH 256 Byte 00H 256 page 00H 00H 12 page Figure 2-5. Data Memory Map The data memory page is indexed by SPR and IDH. In data memory index addressing mode, 16-bit data memory address is composed of two 8-bit SPRs, IDH[7:0] and IDL0[7:0] (or IDH[7:0] and IDL1[7:0]). IDH[7:0] points to a page index, and IDL0[7:0] (or IDL1[7:0]) represents the page offset. In data memory direct addressing mode, an 8-bit direct address, adr[7:0], specifies the offset of the page pointed to by IDH[7:0] (See the details for direct addressing mode in the instruction sections). Unlike the program memory organization, data memory address does not wrap around. In other words, data memory index addressing with modification performs an addition or a subtraction operation on the whole 16-bit address of IDH[7:0] and IDL0[7:0] (or IDL1[7:0]) and updates IDH[7:0] and IDL0[7:0] (or IDL1[7:0]) accordingly. Suppose IDH[7:0] is 0FH and IDL0[7:0] is FCH and the modification on the index registers, IDH[7:0] and IDL0[7:0], is increment by 5H, then, after the modification (i.e., 0FFCH + 5 = 1001H), IDH[7:0] and IDL0[7:0] become 10H and 01H, respectively. As for the MAC816 coprocessor, the data memory is a word unit (16-bit wide) and is divided to X-memory and Ymemory for DSP instruction. The address 0080H in CalmRISC, for example, is viewed as 0040H by MAC816. 2-7 ADDRESS SPACE S3CB519 The S3CB519 has a total of 3072 bytes of data register address from 0080H to 0C7FH. The area from 0000H to 007FH is for peripheral control, and LCD RAM area is from 0C80H to 0CEFH. The MAC816 views the peripheral control register area as being from 0000H to 003FH, and X-memory from 0040H to 043FH, and Y-memory from 0440H to 063FH. In the point of CalmRISC Page 12 Page 11 FFH in Byte Page 0 LCD RAM EFH in Byte In the point of MAC816 063FH in word (0C7FH in Byte) Data Memory 80H 7FH 80H 7FH Y-memory (1 KBytes) 0440H in word (0880H in Byte) 043FH in word (087FH in Byte) Control Register 00H X-memory (2 KBytes) 00H 8 Bits 16 Bits 0040H in word (0080H in Byte) Figure 2-6. S3CB519 Data Memory Map 2-8 S3CB519 REGISTERS 3 OVERVIEW REGISTERS The registers of CalmRISC are grouped into 2 types: general purpose registers and special purpose registers. Table 3-1. General and Special Purpose Registers Registers General Purpose Registers (GPR) Mnemonics R0 R1 R2 R3 Special Purpose Registers (SPR) Group 0 (SPR0) IDL0 IDL1 IDH SR0 Group 1 (SPR1) ILX ILH ILL SR1 Description General Register 0 General Register 1 General Register 2 General Register 3 Lower Byte of Index Register 0 Lower Byte of Index Register 1 Higher Byte of Index Register Status Register 0 Instruction Pointer Link Register for Extended Byte Instruction Pointer Link Register for Higher Byte Instruction Pointer Link Register for Lower Byte Status Register 1 Reset Value Unknown Unknown Unknown Unknown Unknown Unknown Unknown 00H Unknown Unknown Unknown Unknown GPRs can be used in most instructions such as ALU instructions, stack instructions, load instructions, etc .(See the instruction set sections). From the programming standpoint, they have almost no restriction whatsoever. CalmRISC has 4 banks of GPRs, and each bank has 4 registers, R0, R1, R2, and R3. Hence, 16 GPRs in total are available. The GPR bank can be switched by setting an appropriate value in SR0[4:3] (See SR0 for details). The ALU operations between GPRs from different banks are not allowed. SPRs are designed for their own dedicated purposes. They have some restrictions in terms of instructions that can access them. For example, direct ALU operations cannot be performed on SPRs. However, data transfers between a GPR and an SPR are allowed, and stack operations with SPRs are also possible (See the instruction sections for details). 3-1 REGISTERS S3CB519 INDEX REGISTERS: IDH, IDL0 AND IDL1 IDH in concatenation with IDL0 (or IDL1) forms a 16-bit data memory address. Note that CalmRISC's data memory address space is 64 Kbyte (addressable by 16-bit addresses). Basically, IDH points to a page index, and IDL0 (or IDL1) corresponds to an offset of the page. Like GPRs, the index registers are 2-way banked. There are 2 banks in total, each of which has its own index registers, IDH, IDL0 and IDL1. The banks of index registers can be switched by setting an appropriate value in SR0[2] (See SR0 for details). Normally, programmers can reserve an index register pair, IDH and IDL0 (or IDL1), for software stack operations. LINK REGISTERS: ILX, ILH AND ILL The link registers are specially designed for link-and-branch instructions (See LNK and LRET instructions in the instruction sections for details). When an LNK instruction is executed, the current PC[19:0] is saved into ILX, ILH and ILL registers (i.e., PC[19:16] into ILX[3:0], PC[15:8] into ILH [7:0]) and PC[7:0] into ILL[7:0], respectively. When an LRET instruction is executed, the PC value returned is recovered from ILX, ILH, and ILL (i.e., ILX[3:0] into PC[19:16], ILH[7:0] into PC[15:8] and ILL[7:0] into PC[7:0], respectively). These registers are used to access program memory by LDC instructions. When an LDC instruction is executed, the (code) data residing at the program address specified by ILX:ILH:ILL will be read into TBH:TBL. There is a special core input pin signal, nP64KW, which is reserved for indicating that the program memory address space is only 64 Kword. By grounding the signal pin to zero, the upper 4 bits of PC, PC[19:16], is deactivated and therefore its program memory address signals from CalmRISC core are also deactivated. This, in turn, totally eliminates the power consumption due to manipulating the upper 4 bits of PC (See the core pin description section for details). From the programmer's standpoint, when nP64KW is tied to the ground level, then PC[19:16] is not saved into ILX for LNK instructions and ILX is not read back into PC[19:16] for LRET instructions. Therefore, ILX is totally unused in LNK and LRET instructions when nP64KW = 0. 3-2 S3CB519 REGISTERS STATUS REGISTER 0: SR0 SR0 is mainly reserved for system control functions, and each bit of SR0 has its own dedicated function. Table 3-2. Status Register 0 Configuration Flag Name eid ie idb grb[1:0] exe ie0 ie1 Bit 0 1 2 4,3 5 6 7 Description Data memory page selection in direct addressing Global interrupt enable Index register banking selection GPR bank selection Stack overflow/underflow exception enable Interrupt 0 enable Interrupt 1 enable SR0[0] (or eid) selects which page index is to be used in direct addressing. If eid = 0, then page 0 (page index = 0) is used. Otherwise (eid = 1), IDH of the current index register bank is used for the page index. SR0[1] (or ie) is the global interrupt enable flag. As explained in the interrupt/exception section, CalmRISC has 3 interrupt sources (nonmaskable interrupt, interrupt 0, and interrupt 1) and 1 stack exception. Both interrupt 0 and interrupt 1 are masked by setting SR0[1] to 0 (i.e., ie = 0). When an interrupt is serviced, the global interrupt enable flag ie is automatically cleared. The execution of an IRET instruction (return from an interrupt service routine) automatically sets ie = 1. SR0[2] (or idb) and SR0[4:3] (or grb[1:0]) selects an appropriate bank for index registers and GPRs, respectively, as shown below: R3 R2 R1 R0 R3 R3 R2 R3 R2 R1 R2 R1 R0 R1 R0 Bank 3 Bank 2 R0 Bank 1 Bank 0 grb [1:0] idb 11 10 01 00 1 0 IDH IDH IDL0 IDL0 IDL1 IDL1 Figure 3-1. Bank Selection by Setting of GRB Bits and IDB Bit SR0[5] (or exe) enables the stack exception, that is, the stack overflow/underflow exception. If exe = 0, the stack exception is disabled. The stack exception can be used for program debugging in the software development stage. SR0[6] (or ie0) and SR0[7] (or ie1) are enabled, by setting them to 1. Even though ie0 or ie1 are enabled, the interrupts are ignored (not serviced) if the global interrupt enable flag ie is set to 0. 3-3 REGISTERS S3CB519 STATUS REGISTER 1: SR1 SR1 is the register for status flags such as ALU execution flag and stack full flag. Table 3-3. Status Register 1: SR1 Flag Name C V Z N SF - Bit 0 1 2 3 4 5, 6, 7 Carry flag Overflow flag Zero flag Negative flag Stack Full flag Reserved Description SR1[0] (or C) is the carry flag of ALU executions. SR1[1] (or V) is the overflow flag of ALU executions. It is set to 1 if and only if the carry-in into the 8-th bit position of addition/subtraction differs from the carry-out from the 8-th bit position. SR1[2] (or Z) is the zero flag, which is set to 1 if and only if the ALU result is zero. SR1[3] (or N) is the negative flag. Basically, the most significant bit (MSB) of ALU results becomes the N flag. Note, a load instruction into a GPR is considered an ALU instruction. However, if an ALU instruction touches the overflow flag (V) like ADD, SUB, CP, etc, N flag is updated as exclusive-OR of V and the MSB of the ALU result. This implies that even if an ALU operation results in an overflow, N flag is still valid. SR1[4] (or SF) is the stack overflow flag. It is set when the hardware stack is overflowed or underflowed. Programmers can check if the hardware stack has any abnormalities through the stack exception or testing if SF is set (See the hardware stack section for more details). NOTE When an interrupt occurs, the hardware does not save SR0 and SR1, so the software must save the SR1 register values. 3-4 S3CB519 MEMORY MAP 4 OVERVIEW MEMORY MAP To support the control of peripheral hardware, the addresses of peripheral control registers are memory-mapped to page 0 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction at a specific memory location. In this section, detailed descriptions of the S3CB519 control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. This memory area can be accessed with the whole method of data memory access. -- If SR0 bit 0 is "0" then the accessed register area is always page 0. -- If SR0 bit 0 is "1" then the accessed register page is controlled by the proper value of the IDH register. So if you want to access the memory map area, clear the SR0.0 and use the direct addressing mode. This method is used for most cases. The control register is divided into five areas. Here, the system control register area is same in every device. Control Register 7FH Peripheral Control Register ( 1 x 16 or 2 x 8) 70H 6FH Peripheral Control Register (4 x 8) 40H 3FH Port Control Register Area (4 x 8) 20H 1FH Port Data Register Area 10H 0FH System Control Register Area 00H Standard exhortative area Standard area Figure 4-1. Control Register Area 4-1 MEMORY MAP S3CB519 Table 4-1. Control Registers Register Name Mnemonic Decimal Hex Reset R/W Location 16H-1FH is not mapped Port 5 data register Port 4 data register Port 3 data register Port 2 data register Port 1 data register Port 0 data register P5 P4 P3 P2 P1 P0 21 20 19 18 17 16 15H 14H 13H 12H 11H 10H 0FH 00H 00H 00H 00H 00H R R/W R/W R/W R/W R/W Locations 0EH and 0FH are not mapped Watchdog timer control register Basic timer counter Interrupt ID register 1 Interrupt priority register 1 Interrupt mask register 1 Interrupt request register 1 Interrupt ID register 00 Interrupt priority register 00 Interrupt mask register 00 Interrupt request register 00 Oscillator control register Power control register WDTCON BTCNT IIR1 IPR1 IMR1 IRQ1 IIR00 IPR00 IMR00 IRQ00 OSCCON PCON 13 12 11 10 9 8 7 6 5 4 3 2 0DH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H X0H 00H - - 00H - - - 00H - 00H 04H R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W Locations 00H and 01H are not mapped NOTES 1. All the unused and unmapped registers and bits read "0". 2. "-" means undefined. 4-2 S3CB519 MEMORY MAP Table 4-1. Control Registers (Continued) Register Name Mnemonic Decimal Hex Reset R/W Locations 35H-3FH are not mapped Port 5 control register P5CON 52 34H 00H R/W Locations 31H-33H are not mapped Port 4 control register P4CON 48 30H 00H R/W Locations 2DH-2FH are not mapped Port 3 control register P3CON 44 2CH 00H R/W Locations 29H-2BH are not mapped Port 2 control register P2CON 40 28H 00H R/W Locations 26H-27H are not mapped Port 1 interrupt control register Port 1 control register Port 0 interrupt edge control register Port 0 interrupt control register Port 0 control register low Port 0 control register high NOTE: P1INT P1CON P0EDGE P0INT P0CONL P0CONH 37 36 35 34 33 32 25H 24H 23H 22H 21H 20H 00H 00H 00H 00H 00H 00H R/W R/W R/W R/W R/W R/W All unused and unmapped registers and bits read "0". 4-3 MEMORY MAP S3CB519 Table 4-1. Control Registers (Concluded) Register Name D/A converter data register D/A converter control register Battery level detector register Watch timer control register LCD contrast register LCD mode register LCD control register Interrupt ID register 01 Interrupt priority register 01 Interrupt mask register 01 Interrupt request register 01 Timer 0 counter Timer 0 data register Timer 0 control register A/D Converter data register, Low byte A/D Converter data register, High byte A/D Converter control register Serial I/O data register Serial I/O pre-scale register Serial I/O control register Timer B counter Timer B data register Timer B control register Timer A counter Timer A data register Timer A control register NOTES 1. All unused and unmapped registers and bits read "0". 2. "-" means undefined. Mnemonic DADATA DACON BLDCON WTCON LCNST LMOD LCON IIR01 IPR01 IMR01 IRQ01 T0CNT T0DATA T0CON Decimal 115 114 113 112 94 93 92 91 90 89 88 82 81 80 78 77 76 74 73 72 70 69 68 66 65 64 Hex 73H 72H 71H 70H 5EH 5DH 5CH 5BH 5AH 59H 58H 52H 51H 50H 4EH 4DH 4CH 4AH 49H 48H 46H 45H 44H 42H 41H 40H Reset 00H 00H 40H 00H 00H 00H 00H - - 00H - - FFH 00H 00H 00H 00H 00H 00H 00H - FFH 00H - FFH 00H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R R/W R/W R R/W R/W Locations 74H-7FH are not mapped Locations 5FH-6FH are not mapped Locations 53H-57H are not mapped Location 4FH is not mapped ADDATAL ADDATAH ADCON Location 4BH is not mapped SIODATA SIOPS SIOCON Location 47H is not mapped TBCNT TBDATA TBCON Location 43H is not mapped TACNT TADATA TACON 4-4 S3CB519 HARDWARE STACK 5 HARDWARE STACK OVERVIEW The hardware stack in CalmRISC has two usages: -- To save and restore the return PC[19:0] on CALL, CALLS, RET, and IRET instructions. -- Temporary storage space for registers on PUSH and POP instructions. When PC[19:0] is saved into or restored from the hardware stack, the access should be 20 bits wide. On the other hand, when a register is pushed into or popped from the hardware stack, the access should be 8 bits wide. Hence, to maximize the efficiency of the stack usage, the hardware stack is divided into 3 parts: the extended stack bank (XSTACK, 4-bits wide), the odd bank (8-bits wide), and the even bank (8-bits wide). Hardware Stack 3 Level 0 Level 1 Level 2 0 7 0 7 0 5 Stack Pointer SPTR [5:0] 1 0 Stack Level Pointer Odd or Even Bank Selector Level 14 Level 15 XSTACK Odd Bank Even Bank Figure 5-1. Hardware Stack 5-1 HARDWARE STACK S3CB519 The top of the stack (TOS) is pointed to by a stack pointer, called sptr[5:0]. The upper 5 bits of the stack pointer, sptr[5:1], points to the stack level into which either PC[19:0] or a register is saved. For example, if sptr[5:1] is 5H or TOS is 5, then level 5 of XSTACK is empty and either level 5 of the odd bank or level 5 of the even bank is empty. In fact, sptr[0], the stack bank selection bit, indicates which bank(s) is empty. If sptr[0] = 0, both level 5 of the even and the odd banks are empty. On the other hand, if sptr[0] = 1, level 5 of the odd bank is empty, but level 5 of the even bank is occupied. This situation is well illustrated in the figure below. Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 SPTR [5:0] 5 10 001010 Stack Level Pointer Bank Selector Level 15 XSTACK Odd Bank Even Bank Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 SPTR [5:0] 5 10 001011 Stack Level Pointer Bank Selector Level 15 XSTACK Odd Bank Even Bank Figure 5-2. Even and Odd Bank Selection Example As can be seen in the above example, sptr[5:1] is used as the hardware stack pointer when PC[19:0] is pushed or popped and sptr[5:0] as the hardware stack pointer when a register is pushed or popped. Note that XSTACK is used only for storing and retrieving PC[19:16]. Let us consider the cases where PC[19:0] is pushed into the hardware stack (by executing CALL/CALLS instructions or by interrupts/exceptions being served) or is retrieved from the hardware stack (by executing RET/IRET instructions). Regardless of the stack bank selection bit (sptr[0]), TOS of the even bank and the odd bank stores or returns PC[7:0] or PC[15:8], respectively. This is illustrated in the following figures. 5-2 S3CB519 HARDWARE STACK Level 0 SPTR [5:0] 5 10 001010 Stack Level Pointer Level 0 SPTR [5:0] 5 10 001011 Stack Level Pointer Level 5 Level 6 Bank Selector Level 5 Level 6 Bank Selector Level 15 XSTACK Odd Bank Even Bank by Executing CALL, CALLS or Interrupts/Exceptions Level 15 XSTACK Odd Bank Even Bank by Executing CALL, CALLS or Interrupts/Exceptions by Executing RET, IRET by Executing RET, IRET Level 0 SPTR [5:0] 5 10 001100 Stack Level Pointer Level 0 SPTR [5:0] 5 10 001101 Stack Level Pointer Level 5 PC[19:16] Level 6 PC[15:8] PC[7:0] Level 5 PC[19:16] Bank Selector Level 6 PC[7:0] PC[15:8] Bank Selector Level 15 XSTACK Odd Bank Even Bank Level 15 XSTACK Odd Bank Even Bank Figure 5-3. Stack Operation with PC [19:0] As can be seen in the figures, when stack operations with PC[19:0] are performed, the stack level pointer sptr[5:1] (not sptr[5:0]) is either incremented by 1 (when PC[19:0] is pushed into the stack) or decremented by 1 (when PC[19:0] is popped from the stack). The stack bank selection bit (sptr[0]) is unchanged. If a CalmRISC core input signal nP64KW is 0, which signifies that only PC[15:0] is meaningful, then any access to XSTACK is totally deactivated from the stack operations with PC. Therefore, XSTACK has no meaning when the input pin signal, nP64KW, is tied to 0. In that case, XSTACK doesn't have to even exist. As a matter of fact, XSTACK is not included in CalmRISC core itself and it is interfaced through some specially reserved core pin signals (nPUSH, nSTACK, XHSI[3:0], XSHO[3:0]), if the program address space is more than 64K words (See the core pin signal section for details). With regards to stack operations with registers, a similar argument can be made.The only difference is that the data written into or read from the stack are a byte. Hence, the even bank and the odd bank are accessed alternately as shown below. 5-3 HARDWARE STACK S3CB519 Level 0 SPTR [5:0] 5 10 001010 Stack Level Pointer Level 0 SPTR [5:0] 5 10 001011 Stack Level Pointer Level 5 Level 6 Bank Selector Level 5 Level 6 Bank Selector Level 15 XSTACK Odd Bank Even Bank Level 15 XSTACK Odd Bank Even Bank POP Register PUSH Register POP Register PUSH Register Level 0 SPTR [5:0] 5 10 001011 Stack Level Pointer Level 0 SPTR [5:0] 5 10 001100 Stack Level Pointer Level 5 Level 6 Register Level 5 Bank Selector Level 6 Register Bank Selector Level 15 XSTACK Odd Bank Even Bank Level 15 XSTACK Odd Bank Even Bank Figure 5-4. Stack Operation with Registers When the bank selection bit (sptr[0]) is 0, then the register is pushed into the even bank and the bank selection bit is set to 1. In this case, the stack level pointer is unchanged. When the bank selection bit (sptr[0]) is 1, then the register is pushed into the odd bank, the bank selection bit is set to 0, and the stack level pointer is incremented by 1. Unlike the push operations of PC[19:0], any data are not written into XSTACK in the register push operations. This is illustrated in the example figures. When a register is pushed into the stack, sptr[5:0] is incremented by 1 (not the stack level pointer sptr[5:1]). The register pop operations are the reverse processes of the register push operations. When a register is popped out of the stack, sptr[5:0] is decremented by 1 (not the stack level pointer sptr[5:1]). Hardware stack overflow/underflow happens when the MSB of the stack level pointer, sptr[5], is 1. This is obvious from the fact that the hardware stack has only 16 levels and the following relationship holds for the stack level pointer in a normal case. Suppose the stack level pointer sptr[5:1] = 15 (or 01111B in binary format) and the bank selection bit sptr[0] = 1. Here if either PC[19:0] or a register is pushed, the stack level pointer is incremented by 1. Therefore, sptr[5:1] = 16 (or 10000B in binary format) and sptr[5] = 1, which implies that the stack is overflowed. The situation is depicted in the following figure. 5-4 S3CB519 HARDWARE STACK SPTR [5:0] 5 10 011111 Level 0 Level 1 Level 14 Level 15 XSTACK Odd Bank PUSH Register Even Bank PUSH PC [19:0] SPTR [5:0] 5 10 100000 Level 0 Level 1 SPTR [5:0] 5 10 100001 Level 0 Level 1 PC[7:0] Level 14 Level 15 Register XSTACK Odd Bank Even Bank Level 14 Level 15 PC[19:16] PC[15:8] XSTACK Odd Bank Even Bank Figure 5-5. Stack Overflow The first overflow happens due to a register push operation. As explained earlier, a register push operation increments sptr[5:0] (not sptr[5:1]) , which results in sptr[5] = 1, sptr[4:1] = 0 and sptr[0] = 0. As indicated by sptr[5] = 1, an overflow happens. Note that this overflow doesn't overwrite any data in the stack. On the other hand, when PC[19:0] is pushed, sptr[5:1] is incremented by 1 instead of sptr[5:0], and as expected, an overflow results. Unlike the first overflow, PC[7:0] is pushed into level 0 of the even bank and the data that has been there before the push operation is overwritten. A similar argument can be made about stack underflows. Note that any stack operation, which causes the stack to overflow or underflow, doesn't necessarily mean that any data in the stack are lost, as is observed in the first example. In SR1, there is a status flag, SF (Stack Full Flag), which is exactly the same as sptr[5]. In other words, the value of sptr[5] can be checked by reading SF (or SR1[4]). SF is not a sticky flag in the sense that if there was a stack overflow/underflow but any following stack access instructions clear sptr[5] to 0, then SF = 0 and programmers cannot tell whether there was a stack overflow/underflow by reading SF. For example, if a program pushes a register 64 times in a row, sptr[5:0] is exactly the same as sptr[5:0] before the push sequence. Therefore, special attention should be paid. Another mechanism to detect a stack overflow/underflow is through a stack exception. A stack exception happens only when the execution of any stack access instruction results in SF = 1 (or sptr[5] = 1). Suppose a register push operation makes SF = 1 (the SF value before the push operation doesn't matter). Then the stack exception due to the push operation is immediately generated and served If the stack exception enable flag (exe of SR0) is 1. If the stack exception enable flag is 0, then the generated interrupt is not served but pending. Sometime later when the stack exception enable flag is set to 1, the pending exception request is served even if SF = 0. More details are available in the stack exception section. 5-5 HARDWARE STACK S3CB519 NOTES 5-6 S3CB519 EXCEPTIONS 6 OVERVIEW EXCEPTIONS Exceptions in CalmRISC are listed in the table below. Exception handling routines, residing at the given addresses in the table, are invoked when the corresponding exception occurs. The starting address of each exception routine is specified by concatenating 0H (leading 4 bits of 0) and the 16-bit data in the exception vector listed in the table. For example, the interrupt service routine for NMI starts from 0H:PM[00001H]. Note that ":" means concatenation and PM[*] stands for the 16-bit content at the address * of the program memory. Aside from the exception due to reset release, the current PC is pushed in the stack on an exception. When an exception is executed due to NMI/IRQ[1:0]/IEXP, the global interrupt enable flag, ie bit (SR0[1]), is set to 0, whereas ie is set to 1 when IRET or an instruction that explicitly sets ie is executed. Table 6-1. Exceptions Name Reset NMI IRQ[0] IRQ[1] IEXP - - - NOTE: Address 00000H 00001H 00002H 00003H 00004H 00005H 00006H 00007H Priority 1 st 2 nd 4 th 5 th 3 rd - - - Exception due to rest release. Description Exception due to nNMI signal. Non-maskable. Not used. Exception due to nIRQ[0] signal. Maskable by setting ie/ie0. Exception due to nIRQ[1] signal. Maskable by setting ie/ie1. Exception due to stack full. Maskable by setting exe. Reserved. Reserved. Reserved. Break mode due to BKREQ has a higher priority than all the exceptions above. That is, when BKREQ is active, even the exception due to reset release is not executed. HARDWARE RESET When Hardware Reset is active (the reset input signal pin nRES = 0), the control pins in the CalmRISC core are initialized to be disabled, and SR0 and sptr (the hardware stack pointer) are initialized to be 0. Additionally, the interrupt sensing block is cleared. When Hardware Reset is released (nRES = 1), the reset exception is executed by loading the JP instruction in IR (Instruction Register) and 0h:0000h in PC. Therefore, when Hardware Reset is released, the "JP {0h:PM[00000h]}" instruction is executed. When the reset exception is executed, a core output signal nEXPACK is generated to acknowledge the exception. 6-1 EXCEPTIONS S3CB519 NMI EXCEPTION (EDGE SENSITIVE) On the falling edge of a core input signal nNMI, the NMI exception is executed by loading the CALL instruction in IR and 0h:0001h in PC. Therefore, when NMI exception is activated, the "CALL {0h:PM[00001h]}" instruction is executed. When the NMI exception is executed, the ie bit (SR0[1]) becomes 0 and a core output signal nEXPACK is generated to acknowledge the exception. IRQ[0] EXCEPTION (LEVEL-SENSITIVE) When a core input signal nIRQ[0] is low, SR0[6] (ie0) is high, and SR0[1] (ie) is high, IRQ[0] exception is generated, and this will load the CALL instruction in IR (Instruction Register) and 0h:0002h in PC. Therefore, on an IRQ[0] exception, the "CALL {0h:PM[00002h]}" instruction is executed. When the IRQ[0] exception is executed, SR0[1] (ie) is set to 0 and a core output signal nEXPACK is generated to acknowledge the exception. IRQ[1] EXCEPTION (LEVEL-SENSITIVE) When a core input signal nIRQ[1] is low, SR0[7] (ie1) is high, and SR0[1] (ie) is high, IRQ[1] exception is generated, and this will load the CALL instruction in IR (Instruction Register) and 0h:0003h in PC. Therefore, on an IRQ[1] exception, the "CALL {0h:PM[00003h]}" instruction is executed. When the IRQ[1] exception is executed, SR0[1] (ie) is set to 0 and a core output signal nEXPACK is generated to acknowledge the exception. HARDWARE STACK FULL EXCEPTION A Stack Full exception occurs when a stack operation is performed and as a result of the stack operation sptr[5] (SF) is set to 1. If the stack exception enable bit, exe (SR0[5]), is 1, the Stack Full exception is served. One exception to this rule is when nNMI causes a stack operation that sets sptr[5] (SF), since it has higher priority. Handling a Stack Full exception may cause another Stack Full exception. In this case, the new exception is ignored. On a Stack Full exception, the CALL instruction is loaded in IR (Instruction Register) and 0h:0004h in PC. Therefore, when the Stack Full exception is activated, the "CALL {0h:PM[00004h]}" instruction is executed. When the exception is executed, SR0[1] (ie) is set to 0, and a core output signal nEXPACK is generated to acknowledge the exception. BREAK EXCEPTION Break exception is reserved only for an in-circuit debugger. When a core input signal, BKREQ, is high, the CalmRISC core is halted or in the break mode, until BKREQ is deactivated. Another way to drive the CalmRISC core into the break mode is by executing a break instruction, BREAK. When BREAK is fetched, it is decoded in the fetch cycle (IF stage) and the CalmRISC core output signal nBKACK is generated in the second cycle (ID/MEM stage). An in-circuit debugger generates BKREQ active by monitoring nBKACK to be active. BREAK instruction is exactly the same as the NOP (no operation) instruction except that it does not increase the program counter and activates nBKACK in the second cycle (or ID/MEM stage of the pipeline). There, once BREAK is encountered in the program execution, it falls into a deadlock. BREAK instruction is reserved for in-circuit debuggers only, so it should not be used in user programs. 6-2 S3CB519 EXCEPTIONS EXCEPTIONS (or INTERRUPTS) LEVEL NMI VECTOR 0001H SOURCE Not used AD/DA interrupt IVEC0 0002H Timer A match Timer B match SIO External interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 Basic timer overflow Watch timer IVEC1 0003H Timer 0 match Timer 0 overflow KS0 KS1 KS2 KS3 SF_EXCEP 0004H Stack full INT H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W H/W RESET (CLEAR) H/W H/W, S/W H/W, S/W H/W, S/W H/W, S/W NOTES: 1. There are two interrupt vectors, and the one interrupt vector have several interrupt sources. The priority of the sources is controlled by setting the IPR register. 2. IMR00, IPR00, IRQ00, is responsible for AD/DA interrupt, Timer A, Timer B, SIO, External, Basic timer, Watch timer interrupt. IMR01, IPR01, IRQ01 is responsible for INT0-INT6 interrupt. IMR1, IPR1, IRQ1 is responsible for Timer 0 Match, Timer 0 Overflow, Key scan interrupts. 3. External interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting. 4. The NMI has the most higher priority in the interrupt levels. And the priority of SF_EXCEP is next but higher then IVEC0, IVEC1's priority is the last. 5. When system reset occurs, IPR register value is undefined. After reset, the interrupt priority can be changed by setting of IPR register. 6. The pending bit is cleared by Hardware when CPU reads the IIR register value. 7. If you write "LD IIRx, #8H", all bits of IRQx are cleared. (Where x is 1, 00, 01) Figure 6-1. Interrupt Structure 6-3 EXCEPTIONS S3CB519 Clear (when writing clear bit value to bit.2. 1. 0) ex) LD IIR1, #x5H IRQ1.5 is cleared IIR1 Timer 0 Match P1INT.0 KS0 P1INT.1 KS1 P1INT.2 KS2 P1INT.3 KS3 Not used Not used Timer 0 Overflow IRQ1.0 IRQ1.1 IRQ1.2 IRQ1.3 IRQ1.4 IRQ1.5 IRQ1.6 IRQ1.7 IMR1 IPR1 IVEC1 IMR1 Logic IPR1 Logic STOP & IDLE Release CPU AD/DA Interrupt Timer A match Timer B match SIO External Interrupt Basic Timer Watch Timer Not used IRQ00.0 IRQ00.1 IRQ00.2 IRQ00.3 IRQ00.4 IRQ00.5 IRQ00.6 IRQ00.7 IMR00 Logic IPR00 Logic IMR00 IPR00 IVEC0 IIR00 Clear (when writing clear bit value to bit.2. 1. 0) ex) LD IIR00, #x5H IRQ00.5 is cleared INT0 INT1 INT2 INT3 INT4 INT5 INT6 IRQ01.0 IRQ01.1 IRQ01.2 IRQ01.3 IRQ01.4 IRQ01.5 IRQ01.6 IIR01 Clear (when writing clear bit value to bit.2. 1. 0) ex) LD IIR01, #x3H IRQ01.3 is cleared IMR01/ IPR01 Logic Figure 6-2. Interrupt Structure 6-4 S3CB519 EXCEPTIONS INTERRUPT MASK REGISTERS Interrupt Mask Register00 (IMR00) 05H, R/W .7 .6 .5 .4 .3 .2 .1 .0 IRQ00.4 IRQ00.5 IRQ00.6 IRQ00.7 IRQ00.3 Interrupt Mask Register01 (IMR01) 59H, R/W .7 .6 .5 .4 .3 .2 .1 IRQ00.2 IRQ00.1 IRQ00.0 .0 IRQ01.4 IRQ01.5 IRQ01.6 IRQ01.7 IRQ01.3 Interrupt Mask Register1 (IMR1) 09H, R/W .7 .6 .5 .4 .3 .2 .1 IRQ01.2 IRQ01.1 IRQ01.0 .0 IRQ1.4 IRQ1.5 IRQ1.6 IRQ1.7 Interrupt request enable bits: 0 = Disable interrupt request 1 = Enable interrupt request NOTE: IRQ1.3 IRQ1.2 IRQ1.1 IRQ1.0 If you want to change the value of the IMR register, then you first make disable global INT by DI instruction, and change the value of the IMR register. Figure 6-3. Interrupt Mask Register 6-5 EXCEPTIONS S3CB519 INTERRUPT PRIORITY REGISTER IPR Group A IPR Group B IPR Group C IRQx.0 IRQx.1 IRQx.2 IRQx.3 IRQx.4 IRQx.5 IRQx.6 IRQx.7 (note) Interrupt Priority Registers (IPR00:06H, IPR01:5AH, IPR1:0AH, R/W ) .7 .6 .5 .4 .3 .2 .1 .0 Group priority: .7 .4 .1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Not used B>C>A A>B>C B>A>C C>A>B C>B>A A>C>B Not used Group A 0 = IRQx.0 > IRQx.1 1 = IRQx.1 > IRQx.0 Group B 0 = IRQx.2 > (IRQx.3,IRQx.4) 1 = (IRQx.3,IRQx.4) > IRQx.2 Subgroup B 0 = IRQx.3 > IRQx.4 1 = IRQx.4 > IRQx.3 Group C 0 = IRQx.5 > (IRQx.6,IRQx.7) 1 = (IRQx.6,IRQx.7) > IRQx.5 Subgroup C 0 = IRQx.6 > IRQx.7 1 = IRQx.7 > IRQx.6 NOTE: If you want to change the value of the IPR register, then you first make disable global INT by DI instruction, and change the value of the IPR register. Figure 6-4. Interrupt Priority Register 6-6 S3CB519 EXCEPTIONS F PROGRAMMING TIP -- Interrupt Programming Tip 1 Jumped from vector 2 PUSH PUSH LD CP JR CP JR CP JP JP CP JP JP CP JR CP JP JP CP JP JP * LTE05 LTE03 LTE01 SR1 R0 R0, IIR00 R0, #03h ULE, LTE03 R0, #05h ULE, LTE05 R0, #06h EQ, IRQ6_srv T, IRQ7_srv R0, #04 EQ, IRQ4_srv T, IRQ5_srv R0, #01 ULE, LTE01 R0, #02 EQ, IRQ2_srv T, IRQ3_srv R0, #00h EQ, IRQ0_srv T, IRQ1_srv ; service for IRQ0 IRQ0_srv POP POP IRET IRQ1_srv * * R0 SR1 ; service for IRQ1 POP POP IRET * * R0 SR1 IRQ7_srv * * ; service for IRQ7 POP POP IRET NOTE: R0 SR1 If the SR0 register is changed in the interrupt service routine, then the SR0 register must be pushed and popped in the interrupt service routine. 6-7 EXCEPTIONS S3CB519 F PROGRAMMING TIP -- Interrupt Programming Tip 2 Jumped from vector 2 PUSH PUSH PUSH LD SL LD ADD LD LD LRET LJP LJP LJP LJP LJP LJP LJP LJP * * SR1 R0 R1 R0, IIR00 R0 R1, < TBL_INTx R0, > TBL_INTx ILH, R1 ILL, R0 IRQ0_svr IRQ1_svr IRQ2_svr IRQ3_svr IRQ4_svr IRQ5_svr IRQ6_svr IRQ7_svr ; service for IRQ0 TBL_INTx IRQ0_srv POP POP POP IRET IRQ1_srv * * R1 R0 SR1 ; service for IRQ1 POP POP POP IRET * * R1 R0 SR1 IRQ7_srv * * ; service for IRQ7 POP POP POP IRET R1 R0 SR1 NOTES: 1. If the SR0 register is changed in the interrupt service routine, then the SR0 register must be pushed and popped in the interrupt service routine. 2. Above example is assumed that ROM size is less than 64K-word and all the LJP instructions in the jump table (TBL_INTx) is in the same page. 6-8 S3CB519 COPROCESSOR INTERFACE 7 COPROCESSOR INTERFACE OVERVIEW CalmRISC supports an efficient and seamless interface with coprocessors. By integrating a MAC (multiply and accumulate) DSP coprocessor engine with the CalmRISC core, not only the microcontroller functions but also complex digital signal processing algorithms can be implemented in a single development platform (or MDS). CalmRISC has a set of dedicated signal pins, through which data/command/status are exchanged to and from a coprocessor. Depicted below are the coprocessor signal pins and the interface between two processors. Program ROM Data RAM Data Bus [7:0] SYSCP [11:0] nCOPID CalmRISC nCLDID Coprocessor CLDWR EC[2:0] Figure 7-1. Coprocessor Interface Diagram 7-1 COPROCESSOR INTERFACE S3CB519 As shown in the coprocessor interface diagram above, the coprocessor interface signals of CalmRISC are: SYSCP[11:0], nCOPID, nCLDID, nCLDWR, and EC[2:0]. The data are exchanged through data buses, DI[7:0] and DO[7:0]. A command is issued from CalmRISC to a coprocessor through SYSCP[11:0] in COP instructions. The status of a coprocessor can be sent back to CalmRISC through EC[2:0] and these flags can be checked in the condition codes of branch instructions. The coprocessor instructions are listed in the following table Table 7-1. Coprocessor instructions Mnemonic COP CLD CLD JP(or JR) CALL LNK Op 1 #imm:12 GPR imm:8 EC2-EC0 - imm:8 GPR label Op 2 Coprocessor operation Data transfer from coprocessor into GPR Data transfer of GPR to coprocessor Conditional branch with coprocessor status flags Description The coprocessor of CalmRISC does not have its own program memory (i.e., it is a passive coprocessor) as shown in Figure 7 -1. In fact, the coprocessor instructions are fetched and decoded by CalmRISC, and CalmRISC issues the command to the coprocessor through the interface signals. For example, if "COP #imm:12" instruction is fetched, then the 12-bit immediate value (imm:12) is loaded on SYSCP[11:0] signal with nCOPID active in ID/MEM stage, to request the coprocessor to perform the designated operation. The interpretation of the 12-bit immediate value is totally up to the coprocessor. By arranging the 12-bit immediate field, the instruction set of the coprocessor is determined. In other words, CalmRISC only provides a set of generic coprocessor instructions, and its installation to a specific coprocessor instruction set can differ from one coprocessor to another. CLD Write instructions ("CLD imm:8, GPR") put the content of a GPR register of CalmRISC on the data bus (DO[7:0] ) and issue the address(imm:8) of the coprocessor internal register on SYSCP[7:0] with nCLDID active and CLDWR active. CLD Read instructions ("CLD GPR, imm:8" in Table 7-1) work similarly, except that the content of the coprocessor internal register addressed by the 8-bit immediate value is read into a GPR register through DI[7:0] with nCLDID active and CLDWR deactivated. The timing diagram given below is a coprocessor instruction pipeline and shows when the coprocessor performs the required operations. Suppose I2 is a coprocessor instruction. First, it is fetched and decoded by CalmRISC (at t = T(i1)). Once it is identified as a coprocessor instruction, CalmRISC indicates to the coprocessor the appropriate command through the coprocessor interface signals (at t = T(i)). Then the coprocessor performs the designated tasks at t = T(i) and t = T(i+1). Hence IF from CalmRISC and then ID/MEM and EX from the coprocessor constitute the pipeline for I2. Similarly, if I3 is a coprocessor instruction, the coprocessor's ID/MEM and EX stages replace the corresponding stages of CalmRISC. 7-2 S3CB519 COPROCESSOR INTERFACE CalmRISC T (i -1) T (i) T (i +1) I1: Normal Instruction I2: Coprocessor Instruction I3: Coprocessor Instruction Coprocessor Interface Signals IF ID/MEM IF EX ID/MEM IF EX ID/MEM EX For I2 For I 3 Coprocessor I2: I3: ID/MEM EX ID/MEM EX Figure 7-2. Coprocessor Instruction Pipeline In a multi-processor system, the data transfer between processors is an important factor to determine the efficiency of the overall system. Suppose an input data stream is accepted by a processor, in order for the data to be shared by another processors. There should be some efficient mechanism to transfer the data to the processors. In CalmRISC, data transfers are accomplished through a single shared data memory. The shared data memory in a multi-processor has some inherent problems such as data hazards and deadlocks. However, the coprocessor in CalmRISC accesses the shared data memory only at the designated time by CalmRISC at which time CalmRISC is guaranteed not to access the data memory, and therefore there is no contention over the shared data memory. Another advantage of the scheme is that the coprocessor can access the data memory in its own bandwidth. 7-3 COPROCESSOR INTERFACE S3CB519 NOTES 7-4 S3CB519 INSTRUCTION SET 8 OVERVIEW GLOSSARY Notation INSTRUCTION SET This chapter describes the CalmRISC instruction set and the details of each instruction are listed in alphabetical order. The following notations are used for the description. Table 8-1. Instruction Notation Conventions Interpretation Operand N. N can be omitted if there is only one operand. Typically, As additional note, only the affected flags are described in the tables in this section. That is, if a flag is not affected by an operation, it is NOT specified. 8-1 INSTRUCTION SET S3CB519 INSTRUCTION SET MAP Table 8-2.Overall Instruction Set Map IR [15:13,7:2] 000 xxxxxx 001 xxxxxx [12:10]000 ADD GPR, #imm:8 ADD GPR, @idm ADD GPR, adr:8 ADC GPR, adr:8 ADD GPR, GPR ADC GPR, GPR invalid AND GPR, GPR SLA/SL/ RLC/RL/ SRA/SR/ RRC/RR/ GPR 001 SUB GPR, #imm:8 SUB GPR, @idm SUB GPR, adr:8 SBC GPR, adr:8 SUB GPR, GPR SBC GPR, GPR invalid OR GPR, GPR INC/INCC/ DEC/ DECC/ COM/ COM2/ COMC GPR LD GPR, SPR 010 CP GPR, #imm8 CP GPR, @idm CP GPR, adr:8 CPC GPR, adr:8 CP GPR, GPR CPC GPR, GPR invalid XOR GPR, GPR invalid 011 LD GPR, #imm:8 LD GPR, @idm LD GPR, adr:8 LD adr:8, GPR 100 TM GPR, #imm:8 LD @idm, GPR 101 AND GPR, #imm:8 AND GPR, @idm 110 OR GPR, #imm:8 OR GPR, @idm 111 XOR GPR, #imm:8 XOR GPR, @idm 010 xxxxxx BITT adr:8.bs BITS adr:8.bs 011 xxxxxx BITR adr:8.bs BITC adr:8.bs 100 000000 BMS/BMC LD SPR0, #imm:8 invalid AND GPR, adr:8 OR GPR, adr:8 XOR GPR, adr:8 100 000001 100 000010 100 000011 invalid invalid 100 00010x invalid 100 00011x LD SPR, GPR SWAP GPR, SPR invalid LD GPR, GPR LD TBH/TBL, GPR invalid LD GPR, TBH/TBL 100 00100x 100 001010 PUSH SPR POP SPR PUSH GPR POP GPR 8-2 S3CB519 INSTRUCTION SET Table 8-2. Overall Instruction Set Map (Continued) IR 100 001011 [12:10]000 POP 001 invalid 010 LDC 011 invalid 100 LD SPR0, #imm:8 101 AND GPR, adr:8 110 OR GPR, adr:8 111 XOR GPR, adr:8 100 00110x RET/LRET/I RET/NOP/ BREAK invalid LD GPR:bank, GPR:bank invalid invalid invalid invalid 100 00111x 100 01xxxx invalid AND SR0, #imm:8 invalid invalid OR SR0, #imm:8 invalid invalid BANK #imm:2 invalid 100 100000 100 110011 100 1101xx 100 1110xx 100 1111xx [15:10] 101 xxx 110 0xx 110 1xx 111 xxx NOTE: LCALL cc:4, imm:20 (2-word instruction) LLNK cc:4, imm:20 (2-word instruction) LJP cc:4, imm:20 (2-word instruction) JR cc:4, imm:9 CALLS imm:12 LNKS imm:12 CLD GPR, imm:8 / CLD imm:8, GPR / JNZD GPR, imm:8 / SYS #imm:8 / COP #imm:12 "invalid" - invalid instruction. 8-3 INSTRUCTION SET S3CB519 Table 8-3. Instruction Encoding Instruction ADD GPR, #imm:8 SUB GPR, #imm:8 CP GPR, #imm:8 LD GPR, #imm:8 TM GPR, #imm:8 AND GPR, #imm:8 OR GPR, #imm:8 XOR GPR, #imm:8 ADD GPR, @idm SUB GPR, @idm CP GPR, @idm LD GPR, @idm LD @idm, GPR AND GPR, @idm OR GPR, @idm XOR GPR, @idm ADD GPR, adr:8 SUB GPR, adr:8 CP GPR, adr:8 LD GPR, adr:8 BITT adr:8.bs BITS adr:8.bs ADC GPR, adr:8 SBC GPR, adr:8 CPC GPR, adr:8 LD adr:8, GPR BITR adr:8.bs BITC adr:8.bs 011 010 001 15 14 000 13 12 11 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 10 11 000 001 010 011 10 11 bs GPR adr[7:0] bs GPR adr[7:0] GPR idx mod offset[4:0] 10 9 8 7 6 5 4 3 2 1 0 GPR imm[7:0] 8-4 S3CB519 INSTRUCTION SET Table 8-3. Instruction Encoding (Continued) Instruction ADD GPRd, GPRs SUB GPRd, GPRs CP GPRd, GPRs BMS/BMC ADC GPRd, GPRs SBC GPRd, GPRs CPC GPRd, GPRs invalid invalid AND GPRd, GPRs OR GPRd, GPRs XOR GPRd, GPRs invalid ALUop1 ALUop2 invalid LD SPR, GPR LD GPR, SPR SWAP GPR, SPR LD TBL, GPR LD TBH, GPR PUSH SPR POP SPR invalid PUSH GPR POP GPR LD GPRd, GPRs LD GPR, TBL LD GPR, TBH POP LDC @IL LDC @IL+ Invalid NOTE: "x" means not applicable. 15 14 100 13 12 11 000 001 010 011 000 001 010 011 ddd 000 001 010 011 000 001 10 9 8 7 6 5 4 3 2 1 0 GPRd 000000 GPRs 000001 000010 000011 GPR GPR xx GPR GPR GPR GPR 00010 ALUop1 ALUop2 xxx 010-011 000 001 010 011 00011 SPR SPR SPR x x 0 1 SPR SPR xxx x x 000 001 010-011 000 001 010 011 xx xx xx GPR GPR GPRd GPR 00100 001010 GPR GPR GPRs 0 1 x x xx 0 1 x x xx 000 010 xx 001011 001, 011 8-5 INSTRUCTION SET S3CB519 Table 8-3. Instruction Encoding (Concluded) Instruction MODop1 Invalid Invalid AND SR0, #imm:8 OR SR0, #imm:8 BANK #imm:2 15-13 100 12 11 000 001-011 000 001 010 011 10 9 xx xx xx imm[7:6] imm[7:6] xx x imm [1:0] Invalid LCALL cc, imm:20 LLNK cc, imm:20 LJP cc, imm:20 LD SPR0, #imm:8 AND GPR, adr:8 OR GPR, adr:8 XOR GPR, adr:8 JR cc, imm:9 101 imm [8] 8 7 6 5 00110 4 3 2 1 MODop1 xxx 0 2nd word - 01 xxxxxx imm[5:0] xxx 0 xxxx cc 10000000-11001111 1101 imm[19:16] imm[15:0] 1 00 01 10 11 cc SPR0 GPR IMM[7:0] ADR[7:0] - imm[7:0] CALLS imm:12 LNKS imm:12 CLD GPR, imm:8 CLD imm:8, GPR JNZD GPR, imm:8 SYS #imm:8 COP #imm:12 110 0 1 imm[11:0] 111 0 00 01 10 11 GPR GPR GPR xx imm[11:0] imm[7:0] 1 NOTES: 1. "x" means not applicable. 2. There are several MODop1 codes that can be used, as described in table 8-9. 3. The operand 1(GPR) of the instruction JNZD is Bank 3's register. 8-6 S3CB519 INSTRUCTION SET Table 8-4. Index Code Information ("idx") Symbol ID0 ID1 Code 0 1 Index 0 IDH:IDL0 Index 1 IDH:IDL1 Description Table 8-5. Index Modification Code Information ("mod") Symbol @IDx + offset:5 @[IDx - offset:5] Code 00 01 Function DM[IDx], IDx IDx + offset DM[IDx + (2's complement of offset:5)], IDx IDx + (2's complement of offset:5) @[IDx + offset:5]! @[IDx - offset:5]! 10 11 DM[IDx + offset], IDx IDx DM[IDx + (2's complement of offset:5)], IDx IDx NOTE: Carry from IDL is propagated to IDH. In case of @[IDx - offset:5] or @[IDx - offset:5]!, the assembler should convert offset:5 to the 2's complement format to fill the operand field (offset[4:0]). Furthermore, @[IDx - 0] and @[IDx - 0]! are converted to @[IDx + 0] and @[IDx + 0]!, respectively. Table 8-6. Condition Code Information ("cc") Symbol (cc:4) Blank NC or ULT C or UGE Z or EQ NZ or NE OV ULE UGT ZP MI PL ZN SF EC0-EC2 NOTE: Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101-1111 always Function C = 0, unsigned less than C = 1, unsigned greater than or equal to Z = 1, equal to Z = 0, not equal to V = 1, overflow - signed value ~C | Z, unsigned less than or equal to C & ~Z, unsigned greater than N = 0, signed zero or positive N = 1, signed negative ~N & ~Z, signed positive Z | N, signed zero or negative Stack Full EC[0] = 1/EC[1] = 1/EC[2] = 1 EC[2:0] is an external input (CalmRISC core's point of view) and used as a condition. 8-7 INSTRUCTION SET S3CB519 Table 8-7. "ALUop1" Code Information Symbol SLA SL RLC RL SRA SR RRC RR Code 000 001 010 011 100 101 110 111 arithmetic shift left shift left rotate left with carry rotate left arithmetic shift right shift right rotate right with carry rotate right Function Table 8-8. "ALUop2" Code Information Symbol INC INCC DEC DECC COM COM2 COMC - Code 000 001 010 011 100 101 110 111 increment increment with carry decrement decrement with carry 1's complement 2's complement 1's complement with carry reserved Function Table 8-9. "MODop1" Code Information Symbol LRET RET IRET NOP BREAK - - - Code 000 001 010 011 100 101 110 111 return by IL return by HS return from interrupt (by HS) no operation reserved for debugger use only reserved reserved reserved Function 8-8 S3CB519 INSTRUCTION SET QUICK REFERENCE Operation AND OR XOR ADD SUB CP ADC SBC CPC TM BITS BITR BITC BITT BMS/BMC PUSH POP PUSH POP POP - - SPR - - GPR - - GPR R3 #imm:8 adr:8.bs GPR GPR adr:8 op1 GPR op2 adr:8 #imm:8 GPR @idm op1 op1 & op2 op1 op1 | op2 op1 op1 ^ op2 op1 op1 + op2 op1 op1 + ~op2 + 1 op1 + ~op2 + 1 op1 op1 + op2 + c op1 op1 + ~op2 + c op1 + ~op2 + c op1 & op2 op1 (op2[bit] 1) op1 (op2[bit] 0) op1 ~(op2[bit]) z ~(op2[bit]) TF 1 / 0 HS[sptr] GPR, (sptr sptr + 1) GPR HS[sptr - 1], (sptr sptr - 1) HS[sptr] SPR, (sptr sptr + 1) SPR HS[sptr - 1], (sptr sptr - 1) sptr sptr - 2 - Function Flag z,n z,n z,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n z,n z z z z - - z,n - # of word / cycle 1W1C 8-9 INSTRUCTION SET S3CB519 SLA SL RLC RL SRA SR RRC RR INC INCC DEC DECC COM COM2 COMC GPR - c op1[7], op1 {op1[6:0], 0} c op1[7], op1 {op1[6:0], 0} c op1[7], op1 {op1[6:0], c} c op[7], op1 {op1[6:0], op1[7]} c op[0], op1 {op1[7],op1[7:1]} c op1[0], op1 {0, op1[7:1]} c op1[0], op1 {c, op1[7:1]} c op1[0], op1 {op1[0], op1[7:1]} op1 op1 + 1 op1 op1 + c op1 op1 + 0FFh op1 op1 + 0FFh + c op1 ~op1 op1 ~op1 + 1 op1 ~op1 + c c,z,v,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n z,n c,z,v,n c,z,v,n 8-10 S3CB519 INSTRUCTION SET QUICK REFERENCE (Continued) Operation LD LD LD op1 GPR :bank SPR0 GPR op2 GPR :bank #imm:8 GPR SPR adr:8 @idm #imm:8 TBH/TBL GPR GPR GPR - #imm:8 op1 op2 op1 op2 op1 op2 Function Flag z,n - z,n # of word / cycle 1W1C LD LD LD LDC AND OR BANK SWAP LCALL cc SPR TBH/TBL adr:8 @idm @IL @IL+ SR0 op1 op2 op1 op2 op1 op2 (TBH:TBL) PM[(ILX:ILH:ILL)], ILL++ if @IL+ SR0 SR0 & op2 SR0 SR0 | op2 SR0[4:3] op2 op1 op2, op2 op1 (excluding SR0/SR1) If branch taken, push XSTACK, HS[15:0] {PC[15:12],PC[11:0] + 2} and PC op1 else PC[11:0] PC[11:0] + 2 If branch taken, IL[19:0] {PC[19:12], PC[11:0] + 2} and PC op1 else PC[11:0] PC[11:0] + 2 push XSTACK, HS[15:0] {PC[15:12], PC[11:0] + 1} and PC[11:0] op1 IL[19:0] {PC[19:12], PC[11:0] + 1} and PC[11:0] op1 if (Rn == 0) PC PC[delay slot] - 2's complement of imm:8, Rn-else PC PC[delay slot]++, Rn-If branch taken, PC op1 else PC[11:0] < PC[11:0] + 2 If branch taken, PC[11:0] PC[11:0] + op1 else PC[11:0] PC[11:0] + 1 - - - - - 1W2C 1W1C #imm:2 GPR imm:20 - SPR - - - - 2W2C LLNK cc imm:20 - - CALLS LNKS JNZD imm:12 imm:12 Rn - - imm:8 - - - 1W2C LJP cc imm:20 - - 2W2C JR cc imm:9 - - 1W2C NOTE: op1 - operand1, op2 - operand2, 1W1C - 1-Word 1-Cycle instruction, 1W2C - 1-Word 2-Cycle instruction, 2W2C 2-Word 2-Cycle instruction. The Rn of instruction JNZD is Bank 3's GPR. 8-11 INSTRUCTION SET S3CB519 QUICK REFERENCE (Concluded) Operation LRET RET IRET NOP BREAK SYS CLD CLD COP #imm:8 imm:8 GPR #imm:12 - GPR imm:8 - op1 - op2 - PC IL[19:0] PC HS[sptr - 2], (sptr sptr - 2) PC HS[sptr - 2], (sptr sptr - 2) no operation no operation and hold PC no operation but generates SYSCP[7:0] and nSYSID op1 op2, generates SYSCP[7:0], nCLDID, and CLDWR op1 op2, generates SYSCP[7:0], nCLDID, and CLDWR generates SYSCP[11:0] and nCOPID - - z,n - Function Flag - # of word / cycle 1W2C 1W2C 1W2C 1W1C 1W1C 1W1C NOTES: 1. op1 - operand1, op2 - operand2, sptr - stack pointer register, 1W1C - 1-Word 1-Cycle instruction, 1W2C - 1-Word 2-Cycle instruction 2. Pseudo instructions -- SCF/RCF Carry flag set or reset instruction -- STOP/IDLE MCU power saving instructions -- EI/DI Exception enable and disable instructions -- JP/LNK/CALL If JR/LNKS/CALLS commands (1 word instructions) can access the target address, there is no conditional code in the case of CALL/LNK, and the JP/LNK/CALL commands are assembled to JR/LNKS/CALLS in linking time, or else the JP/LNK/CALL commands are assembled to LJP/LLNK/LCALL (2 word instructions) instructions. 8-12 S3CB519 INSTRUCTION SET INSTRUCTION GROUP SUMMARY ALU INSTRUCTIONS "ALU instructions" refer to the operations that use ALU to generate results. ALU instructions update the values in Status Register 1 (SR1), namely carry (C), zero (Z), overflow (V), and negative (N), depending on the operation type and the result. ALUop GPR, adr:8 Performs an ALU operation on the value in GPR and the value in DM[adr:8] and stores the result into GPR. ALUop = ADD, SUB, CP, AND, OR, XOR For SUB and CP, GPR+(not DM[adr:8])+1 is performed. adr:8 is the offset in a specific data memory page. The data memory page is 0 or the value of IDH (Index of Data Memory Higher Byte Register), depending on the value of eid in Status Register 0 (SR0). Operation GPR GPR ALUop DM[00h:adr:8] if eid = 0 GPR GPR ALUop DM[IDH:adr8] if eid = 1 Note that this is an 8-bit operation. Example ADD R0, 80h // Assume eid = 1 and IDH = 01H // R0 R0 + DM[0180h] ALUop GPR, #imm:8 Stores the result of an ALU operation on GPR and an 8-bit immediate value into GPR. ALUop = ADD, SUB, CP, AND, OR, XOR For SUB and CP, GPR+(not #imm:8)+1 is performed. #imm:8 is an 8-bit immediate value. Operation GPR GPR ALUop #imm:8 Example ADD R0, #7Ah // R0 R0 + 7Ah 8-13 INSTRUCTION SET S3CB519 ALUop GPRd, GPRs Store the result of ALUop on GPRs and GPRd into GPRd. ALUop = ADD, SUB, CP, AND, OR, XOR For SUB and CP, GPRd + (not GPRs) + 1 is performed. GPRs and GPRd need not be distinct. Operation GPRd GPRd ALUop GPRs GPRd - GPRs when ALUop = CP (comparison only) Example ADD R0, R1 ALUop GPR, @idm Performs ALUop on the value in GPR and DM[ID] and stores the result into GPR. Index register ID is IDH:IDL (IDH:IDL0 or IDH:IDL1). ALUop = ADD, SUB, CP, AND, OR, XOR For SUB and CP, GPR+(not DM[idm])+1 is performed. idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) Operation GPR - DM[idm] when ALUop = CP (comparison only) GPR GPR ALUop DM[IDx], IDx IDx + offset:5 when idm = IDx + offset:5 GPR GPR ALUop DM[IDx - offset:5], IDx IDx - offset:5 when idm = [IDx - offset:5] GPR GPR ALUop DM[IDx + offset:5] when idm = [IDx + offset:5]! GPR GPR ALUop DM[IDx - offset:5] when idm = [IDx - offset:5]! When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH. Example ADD R0, @ID0+2 ADD R0, @[ID0-2] ADD R0, @[ID1+2]! ADD R0, @[ID1-2]! // assume ID0 = 02FFh // R0 R0 + DM[02FFh], IDH 03h and IDL0 01h // assume ID0 = 0201h // R0 R0 + DM[01FFh], IDH 01h and IDL0 FFh // assume ID1 = 02FFh // R0 R0 + DM[0301], IDH 02h and IDL1 FFh // assume ID1 = 0200h // R0 R0 + DM[01FEh], IDH 02h and IDL1 00h // R0 R0 + R1 8-14 S3CB519 INSTRUCTION SET ALUopc GPRd, GPRs Performs ALUop with carry on GPRd and GPRs and stores the result into GPRd. ALUopc = ADC, SBC, CPC GPRd and GPRs need not be distinct. Operation GPRd GPRd + GPRs + C when ALUopc = ADC GPRd GPRd + (not GPRs) + C when ALUopc = SBC GPRd + (not GPRs) + C when ALUopc = CPC (comparison only) Example ADD R0, R2 ADC R1, R3 SUB R0, R2 SBC R1, R3 CP R0, R2 CPC R1, R3 ALUopc GPR, adr:8 Performs ALUop with carry on GPR and DM[adr:8]. Operation GPR GPR + DM[adr:8] + C when ALUopc = ADC GPR GPR + (not DM[adr:8]) + C when ALUopc = SBC GPR + (not DM[adr:8]) + C when ALUopc = CPC (comparison only) CPLop GPR (Complement Operations) CPLop = COM, COM2, COMC Operation COM GPR COM2 GPR COMC GPR Example COM2 R0 COMC R1 // assume R1:R0 is a 16-bit signed number. // COM2 and COMC can be used to get the 2's complement of it. not GPR (logical complement) not GPR + 1 (2's complement of GPR) not GPR + C (logical complement of GPR with carry) // assume R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. // to add two 16-bit numbers, use ADD and ADC. // assume R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. // to subtract two 16-bit numbers, use SUB and SBC. // assume both R1:R0 and R3:R2 are 16-bit unsigned numbers. // to compare two 16-bit unsigned numbers, use CP and CPC. 8-15 INSTRUCTION SET S3CB519 IncDec GPR (Increment/Decrement Operations) IncDec = INC, INCC, DEC, DECC Operation INC GPR INCC GPR DEC GPR DECC GPR Example INC R0 INCC R1 DEC R0 DECC R1 // assume R1:R0 is a 16-bit number // to increase R1:R0, use INC and INCC. // assume R1:R0 is a 16-bit number // to decrease R1:R0, use DEC and DECC. Increase GPR, i.e., GPR GPR + 1 Increase GPR if carry = 1, i.e., GPR GPR + C Decrease GPR, i.e., GPR GPR + FFh Decrease GPR if carry = 0, i.e., GPR GPR + FFh + C 8-16 S3CB519 INSTRUCTION SET SHIFT/ROTATE INSTRUCTIONS Shift (Rotate) instructions shift (rotate) the given operand by 1 bit. Depending on the operation performed, a number of Status Register 1 (SR1) bits, namely Carry (C), Zero (Z), Overflow (V), and Negative (N), are set. SL GPR Operation 7 C GPR 0 0 Carry (C) is the MSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. SLA GPR Operation 7 C GPR 0 0 Carry (C) is the MSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting. Overflow (V) will be 1 if the MSB of the result is different from C. Z will be 1 if the result is 0. RL GPR Operation 7 C GPR 0 Carry (C) is the MSB of GPR before rotating. Negative (N) is the MSB of GPR after rotatin/g. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. RLC GPR Operation 7 0 GPR C Carry (C) is the MSB of GPR before rotating, Negative (N) is the MSB of GPR after rotating. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. 8-17 INSTRUCTION SET S3CB519 SR GPR Operation 7 0 GPR 0 C Carry (C) is the LSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. SRA GPR Operation 7 GPR 0 C Carry (C) is the LSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting. Overflow (V) is not affected. Z will be 1 if the result is 0. RR GPR Operation 7 GPR 0 C Carry (C) is the LSB of GPR before rotating. Negative (N) is the MSB of GPR after rotating. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. RRC GPR Operation 7 0 GPR C Carry (C) is the LSB of GPR before rotating, Negative (N) is the MSB of GPR after rotating. Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0. 8-18 S3CB519 INSTRUCTION SET LOAD INSTRUCTIONS Load instructions transfer data from data memory to a register or from a register to data memory, or assigns an immediate value into a register. As a side effect, a load instruction placing a value into a register sets the Zero (Z) and Negative (N) bits in Status Register 1 (SR1), if the placed data is 00h and the MSB of the data is 1, respectively. LD GPR, adr:8 Loads the value of DM[adr:8] into GPR. Adr:8 is offset in the page specified by the value of eid in Status Register 0 (SR0). Operation GPR DM[00h:adr:8] if eid = 0 GPR DM[IDH:adr:8] if eid = 1 Note that this is an 8-bit operation. Example LD R0, 80h // assume eid = 1 and IDH= 01H // R0 DM[0180h] LD GPR, @idm Loads a value from the data memory location specified by @idm into GPR. idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) Operation GPR GPR GPR GPR DM[IDx], IDx IDx + offset:5 when idm = IDx + offset:5 DM[IDx - offset:5], IDx IDx - offset:5 when idm = [IDx - offset:5] DM[IDx + offset:5] when idm = [IDx + offset:5]! DM[IDx - offset:5] when idm = [IDx - offset:5]! When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH. Example LD R0, @[ID0 + 03h]! // assume IDH:IDL0 = 0270h // R0 DM[0273h], IDH:IDL0 0270h 8-19 INSTRUCTION SET S3CB519 LD REG, #imm:8 Loads an 8-bit immediate value into REG. REG can be either GPR or an SPR0 group register - IDH (Index of Data Memory Higher Byte Register), IDL0 (Index of Data Memory Lower Byte Register)/ IDL1, and Status Register 0 (SR0). #imm:8 is an 8-bit immediate value. Operation REG #imm:8 Example LD R0 #7Ah LD IDH, #03h LD GPR:bs:2, GPR:bs:2 Loads a value of a register from a specified bank into another register in a specified bank. Example LD R0:1, R2:3 LD GPR, TBH/TBL Loads the value of TBH or TBL into GPR. TBH and TBL are 8-bit long registers used exclusively for LDC instructions that access program memory. Therefore, after an LDC instruction, LD GPR, TBH/TBL instruction will usually move the data into GPRs, to be used for other operations. Operation GPR TBH (or TBL) Example LDC @IL LD R0, TBH LD R1, TBL LD TBH/TBL, GPR Loads the value of GPR into TBH or TBL. These instructions are used in pair in interrupt service routines to save and restore the values in TBH/TBL as needed. Operation TBH (or TBL) GPR LD GPR, SPR Loads the value of SPR into GPR. Operation GPR SPR Example LD R0, IDH // R0 IDH // gets a program memory item residing @ ILX:ILH:ILL // R0 in bank 1, R2 in bank 3 // R0 7Ah // IDH 03h 8-20 S3CB519 INSTRUCTION SET LD SPR, GPR Loads the value of GPR into SPR. Operation SPR GPR Example LD IDH, R0 LD adr:8, GPR Stores the value of GPR into data memory (DM). adr:8 is offset in the page specified by the value of eid in Status Register 0 (SR0). Operation DM[00h:adr:8] GPR if eid = 0 DM[IDH:adr:8] GPR if eid = 1 Note that this is an 8-bit operation. Example LD 7Ah, R0 // assume eid = 1 and IDH = 02h. // DM[027Ah] R0 // IDH R0 LD @idm, GPR Loads a value into the data memory location specified by @idm from GPR. idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) Operation DM[IDx] GPR, IDx IDx + offset:5 when idm = IDx + offset:5 DM[IDx - offset:5] GPR, IDx IDx - offset:5 when idm = [IDx - offset:5] DM[IDx + offset:5] GPR when idm = [IDx + offset:5]! DM[IDx - offset:5] GPR when idm = [IDx - offset:5]! When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH. Example LD @[ID0 + 03h]!, R0 // assume IDH:IDL0 = 0170h // DM[0173h] R0, IDH:IDL0 0170h 8-21 INSTRUCTION SET S3CB519 BRANCH INSTRUCTIONS Branch instructions can be categorized into jump instruction, link instruction, and call instruction. A jump instruction does not save the current PC, whereas a call instruction saves ("pushes") the current PC onto the stack and a link instruction saves the PC in the link register IL. Status registers are not affected. Each instruction type has a 2-word format that supports a 20-bit long jump. JR cc:4, imm:9 imm:9 is a signed number (2's complement), an offset to be added to the current PC to compute the target (PC[19:12]:(PC[11:0] + imm:9)). Operation PC[11:0] PC[11:0] + imm:9 PC[11:0] PC[11:0] + 1 Example L18411: JR Z, 107h LJP cc:4, imm:20 Jumps to the program address specified by imm:20. If program size is less than 64K word, PC[19:16] is not affected. Operation PC[15:0] imm[15:0] if branch taken and program size is less than 64K word PC[19:0] imm[19:0] if branch taken and program size is equal to 64K word or more PC [11:0] PC[11:0] + 1 otherwise Example L18411: LJP Z, 10107h JNZD Rn, imm:8 Jumps to the program address specified by imm:8 if the value of the bank 3 register Rn is not zero. JNZD performs only backward jumps, with the value of Rn automatically decreased. There is one delay slot following the JNZD instruction that is always executed, regardless of whether JNZD is taken or not. Operation If (Rn == 0) PC PC[delay slot] (-) 2's complement of imm:8, Rn Rn - 1 else PC PC[delay slot] + 1, Rn Rn - 1. // assume current PC = 18411h. // next instruction's PC is 10107h If Zero (Z) bit is set // assume current PC = 18411h. // next PC is 18518 (18411h + 107h) if Zero (Z) bit is set. if branch taken (i.e., cc:4 resolves to be true) otherwise 8-22 S3CB519 INSTRUCTION SET Example LOOP_A: * * * // start of loop body JNZD R0, LOOP_A ADD R1, #2 CALLS imm:12 // jump back to LOOP_A if R0 is not zero // delay slot, always executed (you must use one cycle instruction only) Saves the current PC on the stack ("pushes" PC) and jumps to the program address specified by imm:12. The current page number PC[19:12] is not changed. Since this is a 1-word instruction, the return address pushed onto the stack is (PC + 1). If nP64KW is low when PC is saved, PC[19:16] is not saved in the stack. Operation HS[sptr][15:0] current PC + 1 and sptr sptr + 2 (push stack) HS[sptr][19:0] current PC + 1 and sptr sptr + 2 (push stack) PC[11:0] imm:12 Example L18411: CALLS 107h // assume current PC = 18411h. // call the subroutine at 18107h, with the current PC pushed // onto the stack (HS 18412h) if nP64KW = 1. if nP64KW = 0 if nP64KW = 1 LCALL cc:4, imm:20 Saves the current PC onto the stack (pushes PC) and jumps to the program address specified by imm:20. Since this is a 2-word instruction, the return address saved in the stack is (PC + 2). If nP64KW, a core input signal is low when PC is saved, 0000111111PC[19:16] is not saved in the stack and PC[19:16] is not set to imm[19:16]. Operation HS[sptr][15:0] current PC + 2 and sptr + 2 (push stack) if branch taken and nP64KW = 0 HS[sptr][19:0] current PC + 2 and sptr + 2 (push stack) if branch taken and nP64KW = 1 PC[15:0] imm[15:0] if branch taken and nP64KW = 0 PC[19:0] imm[19:0] if branch taken and nP64KW = 1 PC[11:0] PC[11:0] + 2 otherwise Example L18411: LCALL NZ, 10107h // assume current PC = 18411h. // call the subroutine at 10107h with the current PC pushed // onto the stack (HS 18413h) 8-23 INSTRUCTION SET S3CB519 LNKS imm:12 Saves the current PC in IL and jumps to the program address specified by imm:12. The current page number PC[19:12] is not changed. Since this is a 1-word instruction, the return address saved in IL is (PC + 1). If the program size is less than 64K word when PC is saved, PC[19:16] is not saved in ILX. Operation IL[15:0] current PC + 1 IL[19:0] current PC + 1 PC[11:0] imm:12 Example L18411: LNKS 107h // assume current PC = 18411h. // call the subroutine at 18107h, with the current PC saved // in IL (IL[19:0] 18412h) if program size is 64K word or more. if program size is less than 64K word if program size is equal to 64K word or more LLNK cc:4, imm:20 Saves the current PC in IL and jumps to the program address specified by imm:20. Since this is a 2-word instruction, the return address saved in IL is (PC + 2). If the program size is less than 64K word when PC is saved, PC[19:16] is not saved in ILX. Operation IL[15:0] current PC + 2 if branch taken and program size is less than 64K word IL[19:0] current PC + 2 if branch taken and program size is 64K word or more PC[15:0] imm[15:0] if branch taken and program size is less than 64K word PC[19:0] imm[19:0] if branch taken and program size is 64K word or more PC[11:0] PC[11:0] + 2 otherwise Example L18411: LLNK NZ, 10107h // assume current PC = 18411h. // call the subroutine at 10107h with the current PC saved // in IL (IL[19:0] 18413h) if program size is 64K word or more RET, IRET Returns from the current subroutine. IRET sets ie (SR0[1]) in addition. If the program size is less than 64K word, PC[19:16] is not loaded from HS[19:16]. Operation PC[15:0] HS[sptr - 2] and sptr sptr - 2 (pop stack) if program size is less than 64K word PC[19:0] HS[sptr - 2] and sptr sptr - 2 (pop stack) if program size is 64K word or more Example RET // assume sptr = 3h and HS[1] = 18407h. // the next PC will be 18407h and sptr is set to 1h 8-24 S3CB519 INSTRUCTION SET LRET Returns from the current subroutine, using the link register IL. If the program size is less than 64K word, PC[19:16] is not loaded from ILX. Operation PC[15:0] IL[15:0] PC[19:0] IL[19:0] Example LRET // assume IL = 18407h. // the next instruction to execute is at PC = 18407h // if program size is 64K word or more if program size is less than 64K word if program size is 64K word or more JP/LNK/CALL JP/LNK/CALL instructions are pseudo instructions. If JR/LNKS/CALLS commands (1 word instructions) can access the target address, there is no conditional code in the case of CALL/LNK and the JP/LNK/CALL commands are assembled to JR/LNKS/CALLS in linking time or else the JP/LNK/CALL commands are assembled to LJP/LLNK/LCALL (2 word instructions) instructions. 8-25 INSTRUCTION SET S3CB519 BIT MANIPULATION INSTRUCTIONS BITop adr:8.bs Performs a bit operation specified by op on the value in the data memory pointed by adr:8 and stores the result into R3 of current GPR bank or back into memory depending on the value of TF bit. BITop = BITS, BITR, BITC, BITT BITS: bit set BITR: bit reset BITC: bit complement BITT: bit test (R3 is not touched in this case) bs: bit location specifier, 0 - 7. Operation R3 DM[00h:adr:8] BITop bs if eid = 0 R3 DM[IDH:adr:8] BITop bs if eid = 1 (no register transfer for BITT) Set the Zero (Z) bit if the result is 0. Example BITS 25h.3 BITT 25h.3 BMC/BMS Clears or sets the TF bit, which is used to determine the destination of BITop instructions. When TF bit is clear, the result of BITop instructions will be stored into R3 (fixed); if the TF bit is set, the result will be written back to memory. Operation TF 0 TF 1 TM GPR, #imm:8 Performs AND operation on GPR and imm:8 and sets the Zero (Z) and Negative (N) bits. No change in GPR. Operation Z, N flag GPR & #imm:8 BITop GPR.bs Performs a bit operation on GPR and stores the result in GPR. Since the equivalent functionality can be achieved using OR GPR, #imm:8, AND GPR, #imm:8, and XOR GPR, #imm:8, this instruction type doesn't have separate op codes. (BMC) (BMS) // assume eid = 0. set bit 3 of DM[00h:25h] and store the result in R3. // check bit 3 of DM[00h:25h] if eid = 0. 8-26 S3CB519 INSTRUCTION SET AND SR0, #imm:8/OR SR0, #imm:8 Sets/resets bits in SR0 and stores the result back into SR0. Operation SR0 SR0 & #imm:8 SR0 SR0 | #imm:8 BANK #imm:2 Loads SR0[4:3] with #imm[1:0]. Operation SR0[4:3] #imm[1:0] MISCELLANEOUS INSTRUCTION SWAP GPR, SPR Swaps the values in GPR and SPR. SR0 and SR1 can NOT be used for this instruction. No flag is updated, even though the destination is GPR. Operation temp SPR SPR GPR GPR temp Example SWAP R0, IDH // assume IDH = 00h and R0 = 08h. // after this, IDH = 08h and R0 = 00h. PUSH REG Saves REG in the stack (Pushes REG into stack). REG = GPR, SPR Operation HS[sptr][7:0] REG and sptr sptr + 1 Example PUSH R0 // assume R0 = 08h and sptr = 2h // then HS[2][7:0] 08h and sptr 3h 8-27 INSTRUCTION SET S3CB519 POP REG Pops stack into REG. REG = GPR, SPR Operation REG HS[sptr-1][7:0] and sptr sptr - 1 Example POP R0 // assume sptr = 3h and HS[2] = 18407h // R0 07h and sptr 2h POP Pops 2 bytes from the stack and discards the popped data. NOP Does no work but increase PC by 1. BREAK Does nothing and does NOT increment PC. This instruction is for the debugger only. When this instruction is executed, the processor is locked since PC is not incremented. Therefore, this instruction should not be used under any mode other than the debug mode. SYS #imm:8 Does nothing but increase PC by 1 and generates SYSCP[7:0] and nSYSID signals. CLD GPR, imm:8 GPR (imm:8) and generates SYSCP[7:0], nCLDID, and nCLDWR signals. CLD imm:8, GPR (imm:8) GPR and generates SYSCP[7:0], nCLDID, and nCLDWR signals. COP #imm:12 Generates SYSCP[11:0] and nCOPID signals. 8-28 S3CB519 INSTRUCTION SET LDC Loads program memory item into register. Operation [TBH:TBL] PM[ILX:ILH:ILL] [TBH:TBL] PM[ILX:ILH:ILL], ILL++ (LDC @IL) (LDC @IL+) TBH and TBL are temporary registers to hold the transferred program memory items. These can be accessed only by LD GPR and TBL/TBH instruction. Example LD ILX, R1 LD ILH, R2 LD ILL, R3 LDC @IL // assume R1:R2:R3 has the program address to access // get the program data @(ILX:ILH:ILL) into TBH:TBL 8-29 INSTRUCTION SET S3CB519 PSEUDO INSTRUCTIONS EI/DI Exceptions enable and disable instruction. Operation SR0 OR SR0,#00000010b SR0 AND SR0,#11111101b (EI) (DI) Exceptions are enabled or disabled through this instruction. If there is an EI instruction, the SR0.1 is set and reset, when DI instruction. Example DI * * * EI SCF/RCF Carry flag set and reset instruction. Operation CP R0,R0 AND R0,R0 (SCF) (RCF) Carry flag is set or reset through this instruction. If there is an SCF instruction, the SR1.0 is set and reset, when RCF instruction. Example SCF RCF STOP/IDLE MCU power saving instruction. Operation SYS #0Ah SYS #05h (STOP) (IDLE) The STOP instruction stops the both CPU clock and system clock and causes the microcontroller to enter STOP mode. The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Example STOP(or IDLE) NOP NOP NOP * * 8-30 INSTRUCTION SET S3CB519 ADC -- Add with Carry Format: ADC Operation: Flags: . Example: ADC R0, 80h // If eid = 0, R0 R0 + DM[0080h] + C // If eid = 1, R0 R0 + DM[IDH:80h] + C // R0 R0 + R1 + C ADC ADD ADC R0, R1 R0, R2 R1, R3 In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. Even if the result of "ADD R0, R2" is not zero, Z flag can be set to `1' if the result of "ADC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit addition, take care of the change of Z flag. 8-32 S3CB519 INSTRUCTION SET ADD -- Add Format: ADD . Example: Given: IDH:IDL0 = 80FFh, eid = 1 ADD ADD ADD ADD ADD ADD ADD R0, 80h R0, #12h R1, R2 R0, @ID0 + 2 R0, @[ID0 - 3] R0, @[ID0 + 2]! R0, @[ID0 - 2]! // R0 R0 + DM[8080h] // R0 R0 + 12h // R1 R1 + R2 // R0 // R0 // R0 // R0 R0 + DM[80FFh], IDH 81h, IDL0 01h R0 + DM[80FCh], IDH 80h, IDL0 FCh R0 + DM[8101h], IDH 80h, IDL0 FFh R0 + DM[80FDh], IDH 80h, IDL0 FFh In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) 8-33 INSTRUCTION SET S3CB519 AND -- Bit-wise AND Format: AND Example: In the first instruction, if eid bit in SR0 is zero, register R0 has garbage value because data memory DM[0051h-007Fh] are not mapped in S3CB519/S3FB519. In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) 8-34 S3CB519 INSTRUCTION SET AND SR0 -- Bit-wise AND with SR0 Format: Operation: AND SR0, #imm:8 SR0 SR0 & imm:8 AND SR0 performs the bit-wise AND operation on the value of SR0 and imm:8 and stores the result in SR0. Flags: Example: - Given: SR0 = 11000010b nIE nIE0 nIE1 EQU EQU EQU AND AND ~02h ~40h ~80h SR0, #nIE | nIE0 | nIE1 SR0, #11111101b In the first example, the statement "AND SR0, #nIE|nIE0|nIE1" clear all of bits of the global interrupt, interrupt 0 and interrupt 1. On the contrary, cleared bits can be set to `1' by instruction "OR SR0, #imm:8". Refer to instruction OR SR0 for more detailed explanation about enabling bit. In the second example, the statement "AND SR0, #11111101b" is equal to instruction DI, which is disabling interrupt globally. 8-35 INSTRUCTION SET S3CB519 BANK -- GPR Bank selection Format: Operation: Flags: NOTE: BANK #imm:2 SR0[4:3] imm:2 - For explanation of the CalmRISC banked register file and its usage, please refer to chapter 3. Example: BANK LD BANK LD #1 R0, #11h #2 R1, #22h // Select register bank 1 // Bank1's R0 11h // Select register bank 2 // Bank2's R1 22h 8-36 S3CB519 INSTRUCTION SET BITC -- Bit Complement Format: BITC adr:8.bs bs: 3-digit bit specifier Operation: R3 ((adr:8) ^ (2**bs)) (adr:8) ((adr:8) ^ (2**bs)) if (TF == 0) if (TF == 1) BITC complements the specified bit of a value read from memory and stores the result in R3 or back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction. Flags: NOTE: Z: set if result is zero. Reset if not. Since the destination register R3 is fixed, it is not specified explicitly. Given: IDH = 01, DM[0180h] = FFh, eid = 1 BMC BITC BMS BITC // TF 0 // R3 FEh, DM[0180h] = FFh // TF 1 // DM[0180h] FDh Example: 80h.0 80h.1 8-37 INSTRUCTION SET S3CB519 BITR -- Bit Reset Format: BITR adr:8.bs bs: 3-digit bit specifier Operation: R3 ((adr:8) & ((11111111)2 - (2**bs))) (adr:8) ((adr:8) & ((11111111)2 - (2**bs))) if (TF == 0) if (TF == 1) BITR resets the specified bit of a value read from memory and stores the result in R3 or back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction. Flags: NOTE: Z: set if result is zero. Reset if not. Since the destination register R3 is fixed, it is not specified explicitly. Given: IDH = 01, DM[0180h] = FFh, eid = 1 BMC BITR BMS BITR // TF 0 // R3 FDh, DM[0180h] = FFh // TF 1 // DM[0180h] FBh Example: 80h.1 80h.2 8-38 S3CB519 INSTRUCTION SET BITS -- Bit Set Format: BITS adr:8.bs bs: 3-digit bit specifier. Operation: R3 ((adr:8) | (2**bs)) (adr:8) ((adr:8) | (2**bs)) if (TF == 0) if (TF == 1) BITS sets the specified bit of a value read from memory and stores the result in R3 or back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction. Flags: NOTE: Z: set if result is zero. Reset if not. Since the destination register R3 is fixed, it is not specified explicitly. Given: IDH = 01, DM[0180h] = F0h, eid = 1 BMC BITS BMS BITS // TF 0 // R3 0F2h, DM[0180h] = F0h // TF 1 // DM[0180h] F4h Example: 80h.1 80h.2 8-39 INSTRUCTION SET S3CB519 BITT -- Bit Test Format: BITT adr:8.bs bs: 3-digit bit specifier. Operation: Z ~((adr:8) & (2**bs)) BITT tests the specified bit of a value read from memory. Flags: Example: Z: set if result is zero. Reset if not. Given: DM[0080h] = F7h, eid = 0 BITT JR * * * 80h.3 Z, %1 // Z flag is set to `1' // Jump to label %1 because condition is true. %1 BITS NOP * * * 80h.3 8-40 S3CB519 INSTRUCTION SET BMC/BMS - TF bit clear/set Format: Operation: BMS/BMC BMC/BMS clears (sets) the TF bit. TF 0 if BMC TF 1 if BMS TF is a single bit flag which determines the destination of bit operations, such as BITC, BITR, and BITS. Flags: NOTE: - BMC/BMS are the only instructions that modify the content of the TF bit. // TF 1 81h.1 // TF 0 81h.2 R0, R3 Example: BMS BITS BMC BITR LD 8-41 INSTRUCTION SET S3CB519 CALL -- Conditional Subroutine Call (Pseudo Instruction) Format: CALL cc:4, imm:20 CALL imm:12 If CALLS can access the target address and there is no conditional code (cc:4), CALL command is assembled to CALLS (1-word instruction) in linking time, else the CALL is assembled to LCALL (2-word instruction). Operation: Example: CALL * * * C, Wait // HS[sptr][15:0] current PC + 2, sptr sptr + 2 // 2-word instruction // HS[sptr][15:0] current PC + 1, sptr sptr + 2 // 1-word instruction CALL * * * 0088h Wait: NOP NOP NOP NOP NOP RET // Address at 0088h 8-42 S3CB519 INSTRUCTION SET CALLS -- Call Subroutine Format: Operation: CALLS imm:12 HS[sptr][15:0] current PC + 1, sptr sptr + 2 if the program size is less than 64K word. HS[sptr][19:0] current PC + 1, sptr sptr + 2 if the program size is equal to or over 64K word. PC[11:0] imm:12 CALLS unconditionally calls a subroutine residing at the address specified by imm:12. Flags: Example: CALLS * * * - Wait Wait: NOP NOP NOP RET Because this is a 1-word instruction, the saved returning address on stack is (PC + 1). 8-43 INSTRUCTION SET S3CB519 CLD -- Load into Coprocessor Format: CLD imm:8, * * * - 00h 01h 02h 03h CLD CLD CLD CLD AH, R0 AL, R1 BH, R2 BL, R3 // A[15:8] R0 // A[7:0] R1 // B[15:8] R2 // B[7:0] R3 The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816. Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816. 8-44 S3CB519 INSTRUCTION SET CLD -- Load from Coprocessor Format: CLD Example: AH AL BH BL EQU EQU EQU EQU * * * 00h 01h 02h 03h CLD CLD CLD CLD R0, AH R1, AL R2, BH R3, BL // R0 A[15:8] // R1 A[7:0] // R2 B[15:8] // R3 B[7:0] The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816. Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816. 8-45 INSTRUCTION SET S3CB519 COM -- 1's or Bit-wise Complement Format: COM Example: 8-46 S3CB519 INSTRUCTION SET COM2 -- 2's Complement Format: COM2 Example: Given: R0 = 00h, R1 = 5Ah COM2 COM2 R0 R1 // R0 00h, Z and C flags are set to `1'. // R1 A6h, N flag is set to `1'. 8-47 INSTRUCTION SET S3CB519 COMC -- Bit-wise Complement with Carry Format: COMC Example: If register pair R1:R0 is a 16-bit number, then the 2's complement of R1:R0 can be obtained by COM2 and COMC as following. COM2 COMC R0 R1 Note that Z flag do not exactly reflect result of 16-bit operation. For example, if 16-bit register pair R1: R0 has value of FF01h, then 2's complement of R1: R0 is made of 00FFh by COM2 and COMC. At this time, by instruction COMC, zero (Z) flag is set to `1' as if the result of 2's complement for 16bit number is zero. Therefore when programming 16-bit comparison, take care of the change of Z flag. 8-48 S3CB519 INSTRUCTION SET COP -- Coprocessor Format: Operation: Flags: Example: COP COP #0D01h #0234h // generate 1 word instruction code(FD01h) // generate 1 word instruction code(F234h) COP #imm:12 COP passes imm:12 to the coprocessor by generating SYSCP[11:0] and nCOPID signals. - The above two instructions are equal to statement "ELD A, #1234h" for MAC816 operation. The microcode of MAC instruction "ELD A, #1234h" is "FD01F234", 2-word instruction. In this, code `F' indicates `COP' instruction. 8-49 INSTRUCTION SET S3CB519 CP -- Compare Format: CP Example: Given: R0 = 73h, R1 = A5h, IDH:IDL0 = 0123h, DM[0123h] = A5, eid = 1 CP CP CP CP CP CP CP R0, 80h R0, #73h R0, R1 R1, @ID0 R1, @[ID0 - 5] R2, @[ID0 + 7]! R2, @[ID0 - 2]! // C flag is set to `1' // Z and C flags are set to `1' // V flag is set to `1' // Z and C flags are set to `1' In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) 8-50 S3CB519 INSTRUCTION SET CPC -- Compare with Carry Format: CPC Example: If register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers, then use CP and CPC to compare two 16-bit numbers as follows. CP CPC R0, R1 R2, R3 Because CPC considers C when comparing 8-51 INSTRUCTION SET S3CB519 DEC -- Decrement Format: DEC Example: Given: R0 = 80h, R1 = 00h DEC DEC R0 R1 // R0 7Fh, C, V and N flags are set to `1' // R1 FFh, N flags is set to `1' 8-52 S3CB519 INSTRUCTION SET DECC -- Decrement with Carry Format: DECC Example: If register pair R1:R0 is 16-bit signed or unsigned number, then use DEC and DECC to decrement 16-bit number as follows. DEC DECC R0 R1 Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag. 8-53 INSTRUCTION SET S3CB519 DI -- Disable Interrupt (Pseudo Instruction) Format: Operation: DI Disables interrupt globally. It is same as "AND SR0, #0FDh" . DI instruction sets bit1 (ie: global interrupt enable) of SR0 register to "0" - Given: SR0 = 03h DI // SR0 SR0 & 11111101b Flags: Example: DI instruction clears SR0[1] to `0', disabling interrupt processing. 8-54 S3CB519 INSTRUCTION SET EI -- Enable Interrupt (Pseudo Instruction) Format: Operation: EI Enables interrupt globally. It is same as "OR SR0, #02h" . EI instruction sets the bit1 (ie: global interrupt enable) of SR0 register to "1" - Given: SR0 = 01h EI // SR0 SR0 | 00000010b Flags: Example: The statement "EI" sets the SR0[1] to `1', enabling all interrupts. 8-55 INSTRUCTION SET S3CB519 IDLE -- Idle Operation (Pseudo Instruction) Format: Operation: IDLE The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt or reset operation. The IDLE instruction is a pseudo instruction. It is assembled as "SYS #05H", and this generates the SYSCP[7-0] signals. Then these signals are decoded and the decoded signals execute the idle operation. - The next instruction of IDLE instruction is executed, so please use the NOP instruction after the IDLE instruction. Flags: NOTE: Example: IDLE NOP NOP NOP * * * The IDLE instruction stops the CPU clock but not the system clock. 8-56 S3CB519 INSTRUCTION SET INC -- Increment Format: INC Example: Given: R0 = 7Fh, R1 = FFh INC INC R0 R1 // R0 80h, V flag is set to `1' // R1 00h, Z and C flags are set to `1' 8-57 INSTRUCTION SET S3CB519 INCC -- Increment with Carry Format: INCC Example: If register pair R1:R0 is 16-bit signed or unsigned number, then use INC and INCC to increment 16-bit number as following. INC INCC R0 R1 Assume R1:R0 is 0010h, statement "INC R0" increase R0 by one without carry and statement "INCC R1" set zero (Z) flag to `1' as if the result of 16-bit increment is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit increment, take care of the change of Z flag. 8-58 S3CB519 INSTRUCTION SET IRET -- Return from Interrupt Handling Format: Operation: IRET PC HS[sptr - 2], sptr sptr - 2 IRET pops the return address (after interrupt handling) from the hardware stack and assigns it to PC. The ie (i.e., SR0[1]) bit is set to allow further interrupt generation. Flags: NOTE: - The program size (indicated by the nP64KW signal) determines which portion of PC is updated. When the program size is less than 64K word, only the lower 16 bits of PC are updated (i.e., PC[15:0] HS[sptr - 2]). When the program size is 64K word or more, the action taken is PC[19:0] HS[sptr - 2]. Example: SF_EXCEP: NOP * * * // Stack full exception service routine IRET 8-59 INSTRUCTION SET S3CB519 JNZD -- Jump Not Zero with Delay slot Format: JNZD NOTE: - Typically, the delay slot will be filled with an instruction from the loop body. It is noted, however, that the chosen instruction should be "dead" outside the loop for it executes even when the loop is exited (i.e., JNZD is not taken). Given: IDH = 03h, eid = 1 BANK LD LD LD JNZD LD * * * Example: %1 #3 R0, #0FFh R1, #0 IDL0, R0 R0, %B1 @ID0, R1 // R0 is used to loop counter // If R0 of bank3 is not zero, jump to %1. // Clear register pointed by ID0 This example can be used for RAM clear routine. The last instruction is executed even if the loop is exited. 8-60 S3CB519 INSTRUCTION SET JP -- Conditional Jump (Pseudo Instruction) Format: JP cc:4 imm:20 JP cc:4 imm:9 If JR can access the target address, JP command is assembled to JR (1 word instruction) in linking time, else the JP is assembled to LJP (2 word instruction) instruction. There are 16 different conditions that can be used, as described in table 8-6. Operation: Example: %1 LD * * * R0, #10h // Assume address of label %1 is 020Dh JP JP * * * Z, %B1 C, %F2 // Address at 0264h // Address at 0265h %2 LD * * * R1, #20h // Assume address of label %2 is 089Ch In the above example, the statement "JP Z, %B1" is assembled to JR instruction. Assuming that current PC is 0264h and condition is true, next PC is made by PC[11:0] PC[11:0] + offset, offset value is "64h + A9h" without carry. `A9' means 2's complement of offset value to jump backward. Therefore next PC is 020Dh. On the other hand, statement "JP C, %F2" is assembled to LJP instruction because offset address exceeds the range of imm:9. 8-61 INSTRUCTION SET S3CB519 JR -- Conditional Jump Relative Format: JR cc:4 imm:9 cc:4: 4-bit condition code Operation: PC[11:0] PC[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is signextended to 12 bits when added to PC. There are 16 different conditions that can be used, as described in table 8-6. - Unlike LJP, the target address of JR is PC-relative. In the case of JR, imm:9 is added to PC to compute the actual jump address, while LJP directly jumps to imm:20, the target. Flags: NOTE: Example: JR * * * Z, %1 // Assume current PC = 1000h %1 LD * * * R0, R1 // Address at 10A5h After the first instruction is executed, next PC has become 10A5h if Z flag bit is set to `1'. The range of the relative address is from +255 to -256 because imm:9 is signed number. 8-62 S3CB519 INSTRUCTION SET LCALL -- Conditional Subroutine Call Format: Operation: LCALL cc:4, imm:20 HS[sptr][15:0] current PC + 2, sptr sptr + 2, PC[15:0] imm[15:0] if the condition holds and the program size is less than 64K word. HS[sptr][19:0] current PC + 2, sptr sptr + 2, PC[19:0] imm:20 if the condition holds and the program size is equal to or over 64K word. PC[11:0] PC[11:0] + 2 otherwise. LCALL instruction is used to call a subroutine whose starting address is specified by imm:20. Flags: Example: LCALL LCALL L1 C, L2 - Label L1 and L2 can be allocated to the same or other section. Because this is a 2-word instruction, the saved returning address on stack is (PC + 2). 8-63 INSTRUCTION SET S3CB519 LD adr:8 -- Load into Memory Format: LD adr:8, If eid bit of SR0 is zero, the statement "LD 80h, R0" load value of R0 into DM[0080h], else eid bit was set to `1', the statement "LD 80h, R0" load value of R0 into DM[0180h] 8-64 S3CB519 INSTRUCTION SET LD @idm -- Load into Memory Indexed Format: LD @idm, In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) 8-65 INSTRUCTION SET S3CB519 LD -- Load Register Format: LD Example: In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) 8-66 S3CB519 INSTRUCTION SET LD -- Load GPR:bankd, GPR:banks Format: LD Example: LD LD R2:1, R0:3 R0:0, R0:2 8-67 INSTRUCTION SET S3CB519 LD -- Load GPR, TBH/TBL Format: LD Example: 8-68 S3CB519 INSTRUCTION SET LD -- Load TBH/TBL, GPR Format: LD 8-69 INSTRUCTION SET S3CB519 LD SPR Format: -- Load SPR LD Operation: Flags: Example: - Given: register pair R1:R0 = 1020h LD LD ILH, R1 ILL, R0 // ILH 10h // ILL 20h 8-70 S3CB519 INSTRUCTION SET LD SPR0 -- Load SPR0 Immediate Format: Operation: LD SPR0, #imm:8 SPR0 imm:8 LD SPR0 loads an 8-bit immediate value into SPR0. Flags: Example: - Given: eid = 1, idb = 0 (index register bank 0 selection) LD LD LD LD IDH, #80h IDL1, #44h IDL0, #55h SR0, #02h // IDH point to page 80h The last instruction set ie (global interrupt enable) bit to `1'. Special register group 1 (SPR1) registers are not supported in this addressing mode. 8-71 INSTRUCTION SET S3CB519 LDC -- Load Code Format: LDC // Loads value of PM[ILX:ILH:ILL] into TBH:TBL // Move data in TBH:TBL to GPRs for further processing The statement "LDC @IL" do not increase, but if you use statement "LDC @IL+", ILL register is increased by one after instruction execution. 8-72 S3CB519 INSTRUCTION SET LJP -- Conditional Jump Format: LJP cc:4, imm:20 cc:4: 4-bit condition code Operation: PC[15:0] imm[15:0] if condition is true and the program size is less than 64K word. If the program is equal to or larger than 64K word, PC[19:0] imm[19:0] as long as the condition is true. There are 16 different conditions that can be used, as described in table 8-6. - LJP cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target address of the jump. Flags: NOTE: Example: LJP * * * C, %1 // Assume current PC = 0812h %1 LD * * * R0, R1 // Address at 10A5h After the first instruction is executed, LJP directly jumps to address 10A5h if condition is true. 8-73 INSTRUCTION SET S3CB519 LLNK -- Linked Subroutine Call Conditional Format: LLNK cc:4, imm:20 cc:4: 4-bit condition code Operation: If condition is true, IL[19:0] {PC[19:12], PC[11:0] + 2}. Further, when the program is equal to or larger than 64K word, PC[19:0] imm[19:0] as long as the condition is true. If the program is smaller than 64K word, PC[15:0] imm[15:0]. There are 16 different conditions that can be used, as described in table 8-6. Flags: NOTE: - LLNK is used to conditionally to call a subroutine with the return address saved in the link register (IL) without stack operation. This is a 2-word instruction. Example: LLNK NOP * * * Z, %1 // Address at 005Ch, ILX:ILH:ILL 00:00:5Eh // Address at 005Eh %1 LD * * * R0, R1 LRET 8-74 S3CB519 INSTRUCTION SET LNK -- Linked Subroutine Call (Pseudo Instruction) Format: LNK cc:4, imm:20 LNK imm:12 If LNKS can access the target address and there is no conditional code (cc:4), LNK command is assembled to LNKS (1 word instruction) in linking time, else the LNK is assembled to LLNK (2 word instruction). Operation: Example: LNK LNK NOP * * * Z, Link1 Link2 // Equal to "LLNK Z, Link1" // Equal to "LNKS Link2" Link2: NOP * * * LRET Subroutines section CODE, ABS 0A00h Subroutines Link1: NOP * * * LRET 8-75 INSTRUCTION SET S3CB519 LNKS -- Linked Subroutine Call Format: Operation: LNKS imm:12 IL[19:0] {PC[19:12], PC[11:0] + 1} and PC[11:0] imm:12 LNKS saves the current PC in the link register and jumps to the address specified by imm:12. - LNKS is used to call a subroutine with the return address saved in the link register (IL) without stack operation. Flags: NOTE: Example: LNKS NOP * * * Link1 // Address at 005Ch, ILX:ILH:ILL 00:00:5Dh // Address at 005Dh Link1: NOP * * * LRET 8-76 S3CB519 INSTRUCTION SET LRET -- Return from Linked Subroutine Call Format: Operation: LRET PC IL[19:0] LRET returns from a subroutine by assigning the saved return address in IL to PC. - Flags: Example: Link1: LNK NOP * * * Link1 LRET ; PC[19:0] ILX:ILH:ILL 8-77 INSTRUCTION SET S3CB519 NOP -- No Operation Format: Operation: NOP No operation. When the instruction NOP is executed in a program, no operation occurs. Instead, the instruction time is delayed by approximately one machine cycle per each NOP instruction encountered. Flags: Example: - NOP 8-78 S3CB519 INSTRUCTION SET OR -- Bit-wise OR Format: OR Flags: Example: In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more detailed explanation about this addressing mode. idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1) 8-79 INSTRUCTION SET S3CB519 OR SR0 -- Bit-wise OR with SR0 Format: Operation: OR SR0, #imm:8 SR0 SR0 | imm:8 OR SR0 performs the bit-wise OR operation on SR0 and imm:8 and stores the result in SR0. Flags: Example: - Given: SR0 = 00000000b EID IE IDB1 IE0 IE1 EQU EQU EQU EQU EQU OR OR 01h 02h 04h 40h 80h SR0, #IE | IE0 | IE1 SR0, #00000010b In the first example, the statement "OR SR0, #EID|IE|IE0" set global interrupt(ie), interrupt 0(ie0) and interrupt 1(ie1) to `1' in SR0. On the contrary, enabled bits can be cleared with instruction "AND SR0, #imm:8". Refer to instruction AND SR0 for more detailed explanation about disabling bit. In the second example, the statement "OR SR0, #00000010b" is equal to instruction EI, which is enabling interrupt globally. 8-80 S3CB519 INSTRUCTION SET POP -- POP Format: Operation: POP sptr sptr - 2 POP decrease sptr by 2. The top two bytes of the hardware stack are therefore invalidated. Flags: Example: - Given: sptr[5:0] = 001010b POP This POP instruction decrease sptr[5:0] by 2. Therefore sptr[5:0] is 001000b. 8-81 INSTRUCTION SET S3CB519 POP -- POP to Register Format: POP Example: POP POP R0 IDH In the first instruction, value of HS[sptr-1] is loaded to R0 and the second instruction "POP IDH" load value of HS[sptr-1] to register IDH. Refer to chapter 5 for more detailed explanation about POP operations for hardware stack. 8-82 S3CB519 INSTRUCTION SET PUSH -- Push Register Format: PUSH In the first instruction, value of register R0 is loaded to HS[sptr-1] and the second instruction "PUSH IDH" load value of register IDH to HS[sptr-1]. Current HS pointed by stack point sptr[5:0] be emptied. Refer to chapter 5 for more detailed explanation about PUSH operations for hardware stack. 8-83 INSTRUCTION SET S3CB519 RET -- Return from Subroutine Format: Operation: RET PC HS[sptr - 2], sptr sptr - 2 RET pops an address on the hardware stack into PC so that control returns to the subroutine call site. Flags: Example: - Given: sptr[5:0] = 001010b CALLS * * * Wait // Address at 00120h Wait: NOP NOP NOP NOP NOP RET // Address at 01000h After the first instruction CALLS execution, "PC+1", 0121h is loaded to HS[5] and hardware stack pointer sptr[5:0] have 001100b and next PC became 01000h. The instruction RET pops value 0121h on the hardware stack HS[sptr-2] and load to PC then stack pointer sptr[[5:0] became 001010b. 8-84 S3CB519 INSTRUCTION SET RL -- Rotate Left Format: RL Example: 8-85 INSTRUCTION SET S3CB519 RLC -- Rotate Left with Carry Format: RLC Example: In the second example, assuming that register pair R1:R0 is 16-bit number, then RL and RLC are used for 16-bit rotate left operation. But note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag. 8-86 S3CB519 INSTRUCTION SET RR -- Rotate Right Format: RR Example: 8-87 INSTRUCTION SET S3CB519 RRC -- Rotate Right with Carry Format: RRC Example: In the second example, assuming that register pair R1:R0 is 16-bit number, then RR and RRC are used for 16-bit rotate right operation. But note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag. 8-88 S3CB519 INSTRUCTION SET SBC -- Subtract with Carry Format: SBC Example: SBC R0, 80h // If eid = 0, R0 R0 + ~DM[0080h] + C // If eid = 1, R0 R0 + ~DM[IDH:80h] + C // R0 R0 + ~R1 + C SBC SUB SBC R0, R1 R0, R2 R1, R3 In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers. Even if the result of "ADD R0, R2" is not zero, zero (Z) flag can be set to `1' if the result of "SBC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit addition, take care of the change of Z flag. 8-89 INSTRUCTION SET S3CB519 SL -- Shift Left Format: SL Example: 8-90 S3CB519 INSTRUCTION SET SLA -- Shift Left Arithmetic Format: SLA |